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4 layers65 × 60 mmReworkctf reworkctf, the printed circuit board in 3D

Reworkctf reworkctf

PCBench/PCBench21

resolution = [0.5, 0.5] pcbfolder = '../PCBs/' pcbnames = ["1Bitsy1bitsy"] iters = 30 env = PCBRoutingEnv(resolution=resolution, pcbfolder=pcbfolder, pcbnames=pcbnames) obs, info = env.reset() for in range(iters): act =…

Size
65 × 60 mm
Copper layers
4
Thickness
1.6 mm
Parts
143
Nets
250
Pads
588
Tracks, vias
2,143, 122
Routed
Yes
KiCad
KiCad 5 (file 20171130)
Created
28 Mar 2023
Updated
18 Jan 2024

Overview

Reworkctf reworkctf is an open-source printed circuit board by PCBench, from the PCBench/PCBench repository on GitHub, published under the MIT licence. It is a 4-layer board of 65 × 60 mm with 143 parts on 250 nets, routed with 2,143 tracks and 122 vias.

It is built around the XC3S50A-4FTG256C, 74HC04D and ADP322ACPZ-145-R7. Its parts include 51 resistors, 45 capacitors, 23 diodes, 6 ICs and 2 connectors. It belongs with the FPGA and CPLD boards of this library.

Main components

3

README

README.md

PCBench: A Dataset for Printed Circuit Board Routing

PCBench is a dataset for PCB routing task, it includes a dataset consisting of 164 printed circuit boards (PCB), a data augmentation script to expand the dataset for supervised learning (SL) tasks, and a reinforcement learning (RL) environment.

Dataset

Folder Structure

All the PCB designs in our dataset are stored in the folder PCBs, where each PCB design is stored in a subfolder named {author/org}_{PCB_name}_{design_version(optional)}. Below is the folder structure of the dataset.

text
├── PCBs
│   ├── master_metadata.json
│   ├── subfolder1
│   │   ├── raw.kicad_pcb
│   │   ├── processed.kicad_pcb
│   │   ├── final.json
│   │   ├── metadata.json
│   │   ├── visual.png
│   ├── subfolder2
│   │   ├── raw.kicad_pcb
│   │   ├── processed.kicad_pcb
│   │   ├── final.json
│   │   ├── metadata.json
│   │   ├── visual.png
│   ├── ...

The raw.kicad_pcb is the raw PCB design file, process.kicad_pcb is the file after cleaning up, final.json stores only routing-related information used for ML tasks. metadata.json stores the meta information for each single PCB design. visual.png is a visualization of each single PCB design. master_meta.json contains metadata of all PCBs and global-level information.

PCB Routing Description Language (PCB-RDL)

We propose a JSON specification (final.json for each PCB design) called the PCB Routing Description Language (PCB-RDL) that expresses a PCB routing problem and its solutions intuitively using basic concepts in order to facilitate research into automated PCB routing using ML. Following figure shows is an example of PCB with marked components in PCB-RDL (Left) and it corrsponding PCB-RDL (Right).

PCB example

Data Augmentation

Run

The augmentation data can be generated with the script Scripts/Data_augmentation/augmentation.py. To generate 3 samples by randomly extracting 50% nets from the PCB 1Bitsy_1bitsy, please run the following command

text
cd Scripts/Data_augmentation/
python augmentation.py --num_samples 3 --net_ratio 0.5 --pcb_name 1Bitsy_1bitsy

Output

All the generated PCBs will be stored in the folder named augmented_data under Scripts/Data_augmentation/. In augmented_data, all the generated samples will be stored in a subfolder with the name of selected PCB. Each generated sample has the name sample_index.json. For example, the above command will generate the following file under Scripts/Data_augmentation/

text
├── augmented_data
│   ├── 1Bitsy_1bitsy
│   │   ├── 1.json
│   │   ├── 2.json
│   │   ├── 3.json

RL environment

Installation

The RL environment requires Python >= 3.7. You can simply install the environment with the following commands:

text
git clone https://github.com/PCBench/PCBench.git
cd PCBench
python setup.py install

After installation, open a Python console and type

text
from RLEnv.EnvLayer.PCBRoutingEnv import PCBRoutingEnv

If no error occurs, you have successfully installed the PCB routing environment.

API Usage

The following content shows an example of API usage of PCBRoutingEnv.

text
from RLEnv.EnvLayer.PCBRoutingEnv import PCBRoutingEnv
import random

resolution = [0.5, 0.5]
pcb_folder = '../PCBs/'
pcb_names = ["1Bitsy_1bitsy"]
iters = 30
env = PCBRoutingEnv(resolution=resolution, pcb_folder=pcb_folder, pcb_names=pcb_names)
obs, info = env.reset()
for _ in range(iters):
    act = random.randint(0,5)
    obs, rew, terminal, _, info = env.step(act)
    if terminal:
        env.reset()

You can find more examples of customizing functions of reward and state observation from RLEnv/examples.ipynb.

Parts

143
QtyValueFootprintReferences
300.1 uFazonenberg_pcb:EIA_0402_CAP_NOSILKC10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C28, C30, C31, C32, C33, C34 +14
23470azonenberg_pcb:EIA_0402_RES_NOSILKR11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26 +7
23GREENazonenberg_pcb:EIA_0603_LEDD1, D2, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23 +7
154.7 uFazonenberg_pcb:EIA_0603_CAP_NOSILKC1, C2, C3, C4, C20, C21, C22, C23, C24, C25, C26, C27, C29, C40, C41
131Kazonenberg_pcb:EIA_0402_RES_NOSILKR1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R28, R29, R52
11270azonenberg_pcb:EIA_0402_RES_NOSILKR31, R32, R33, R35, R36, R37, R38, R39, R41, R42, R43
6VIAPADazonenberg_pcb:TESTPOINT_SMT_0.5MMW1, W2, W3, W4, W5, W6
2TESTPOINT_BARETRACE_150UMazonenberg_pcb:TESTPOINT_BARETRACE_150UMLEVEL2_SHORT, LEVEL5_SHORT
10azonenberg_pcb:EIA_0201_RES_NOSILKR45
10azonenberg_pcb:EIA_0402_RES_NOSILKR44
10azonenberg_pcb:EIA_0805_CAP_NOSILKR30
11 MHzazonenberg_pcb:OSCILLATOR_3.2x2.5U4
1270azonenberg_pcb:EIA_01005_RES_NOSILKR40
174HC04azonenberg_pcb:TSSOP_14_0.65MM_5p6MM_NOPINS_1_2U6
174HC04azonenberg_pcb:SOIC_14_3.9MM_NOPIN11U3
1ADP322ACPZ-145-R7azonenberg_pcb:QFN_16_0.5MM_3x3MMU5
1LOGOw_logo:Logo_silk_OSHW_6x6mmG***_2
1LOGOw_logo:Logo_silk_WEEE_3.4x5mmG***_4
1LOGOw_logo:Logo_silk_ROHS_5x2.8mmG***_3
1LOGOazonenberg_pcb:LONGTHING-1200DPIG***
1UX60SX-MB-5STazonenberg_pcb:CONN_HIROSE_UX60S-MB-5ST_MINI_USBJ2
1W25Q80BVazonenberg_pcb:SOIC_8_3.9MMU2
1XC3S50A-4FTG256Cazonenberg_pcb:BGA_256_17x17_FULLARRAY_1MMU1
1XILINX_JTAGazonenberg_pcb:XILINX_JTAG_PTH_MOLEX_0878311420J1

The 139 most common of 143 parts.

Questions

How big is the Reworkctf reworkctf PCB?

It measures 65 × 60 mm and has 4 copper layers, 1.6 mm thick.

What parts does the Reworkctf reworkctf use?

143 parts, built around the XC3S50A-4FTG256C, 74HC04D and ADP322ACPZ-145-R7. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the Reworkctf reworkctf KiCad files?

From the PCBench/PCBench repository on GitHub, at the commit this page was made from: the board is PCBs/reworkctf_reworkctf/processed.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.

Can I use the Reworkctf reworkctf design in my own project?

Its repository publishes it under the MIT licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).

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