2 layers80 × 50 mm

Aegis imu carrier
krishharma/aegis-mtstdp
Integer STDP continual-learning core for FPGA (Python golden model + Verilog). Tiny-net co-sim. IMU/power carrier PCB. Tables are simulator results. Not an ASIC.
27 parts
Printed circuit boards designed in KiCad and published on GitHub, each with its parts, layers and size, its README and its files; open any of them in PCBKit.

krishharma/aegis-mtstdp
Integer STDP continual-learning core for FPGA (Python golden model + Verilog). Tiny-net co-sim. IMU/power carrier PCB. Tables are simulator results. Not an ASIC.