2 layers80 × 50 mm Aegis imu carrier, the printed circuit board in 3D

Aegis imu carrier

Integer STDP continual-learning core for FPGA (Python golden model + Verilog). Tiny-net co-sim. IMU/power carrier PCB. Tables are simulator results. Not an ASIC.

Open in PCBKit

Size: 80 × 50 mm
Copper layers: 2
Thickness: 1.6 mm
Parts: 27
Nets: 11
Pads: 78
Tracks, vias: 78, 10
Pours: 2
Routed: Yes
KiCad: KiCad 10.0 (file 20260206)
Created: 10 Sep 2026
Updated: 16 Sep 2026

Overview

Aegis imu carrier is an open-source printed circuit board by krishharma, from the krishharma/aegis-mtstdp repository on GitHub. It is a 2-layer board of 80 × 50 mm with 27 parts on 11 nets, routed with 78 tracks and 10 vias.

It is built around the INA219AID, AP2112K-3.3 and M2.5, with the SS14 among its other parts. Its parts include 5 resistors, 4 capacitors, 4 connectors, 3 diodes and 2 ICs. It belongs with the fPGA and programmable logic and sensors and measurement boards and the FPGA and CPLD boards of this library.

Main components

README

pcb/README.md

Aegis IMU / power carrier (KiCad 10)

Open aegis_imu_carrier.kicad_pro. This is a 2-layer FPGA harness, not an ASIC.

Regenerate (source of truth):

bash

make kicad
# or:
python3 pcb/gen_kicad.py
python3 pcb/run_kicad.py

run_kicad.py upgrades the files for KiCad 10, runs ERC/DRC, fills GND zones, and writes Gerbers.

File	What it is
`aegis_imu_carrier.kicad_sch`	Wired schematic (power OR, LDO, shunt/INA219, I2C, connectors)
`aegis_imu_carrier.kicad_pcb`	80 × 50 mm board, footprints, traces, filled GND zones
`bom.csv`	Fab / buy list
`gerbers/`	Gerber + Excellon drill + centroid (after `make kicad`)
`reports/`	ERC/DRC JSON, schematic PDF, board SVG
`preview.png`	Layout sketch (not a Gerber)

What is on the board

J1 Digilent PMOD 2×6 → PYNQ-Z2 / Arty JA
- Pin 1 UART (FPGA Y18) — not used by the IMU; leave as a probe
- Pin 2 SCL (Y19) Pin 3 SDA (Y16)
- Pin 5 / 11 GND
- Pins 6 / 12 FPGA 3V3 unconnected so the onboard LDO and the FPGA 3V3 do not fight
J2 GY-521 (MPU-6050) 1×8: VCC GND SCL SDA XDA XCL AD0 INT. AD0 strapped to GND → I2C 0x68
JUSB Micro-B + J4 5 V header, Schottky-ORed with J3 1S LiPo into VSYS
U1 AP2112K-3.3 (SOT-23-5) → +3V3_REG → R5 10 mΩ → +3V3 load rail
U2 INA219 (SOIC-8) high-side on that shunt, A0=A1=GND → 0x40
4.7 kΩ I2C pull-ups, 3V3 LED, decoupling, four M2.5 holes

J3 is discharge only. There is no charger. Do not feed USB 5 V into a LiPo.

INA219 current is board-level. Do not quote it as ASIC milliwatts.

Fab (JLCPCB / PCBWay)

make kicad fills zones and writes pcb/gerbers/. Stackup: FR4 1.6 mm, 2-layer, 1 oz, HASL or ENIG, 0.25 mm min track, vias 0.8 / 0.4 mm.

Hand-solder is intended: 0402 pull-ups are the smallest parts; 0805 / SOIC-8 / SOT-23-5 are student-friendly.

Bring-up

Power USB 5 V (or J4). LED D1 on. +3V3 ≈ 3.3 V at J2 pin 1.
PMOD cable JA → J1 (pin 1 marked).
Plug GY-521 onto J2. I2C scan: 0x68 (IMU), 0x40 (INA219).
Load mtstdp_fpga_top. LEDs = class; UART on JA pin 1 = ASCII '0'/'1'.

Parts

Qty	Value	Footprint	References
4	M2.5	MountingHole:MountingHole_2.5mm	H1, H2, H3, H4
2	100n	Capacitor_SMD:C_0402_1005Metric	C3, C4
2	10uF	Capacitor_SMD:C_0805_2012Metric	C1, C2
2	4.7k	Resistor_SMD:R_0402_1005Metric	R1, R2
2	SS14	Diode_SMD:D_SOD-123	D2, D3
1	+3V3	TestPoint:TestPoint_Pad_D1.5mm	TP1
1	10k	Resistor_SMD:R_0402_1005Metric	R3
1	10m	Resistor_SMD:R_1206_3216Metric	R5
1	1k	Resistor_SMD:R_0402_1005Metric	R4
1	5V AUX	Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical	J4
1	AP2112K-3.3	Package_TO_SOT_SMD:SOT-23-5	U1
1	GND	TestPoint:TestPoint_Pad_D1.5mm	TP2
1	GREEN	LED_SMD:LED_0603_1608Metric	D1
1	GY-521	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J2
1	INA219AID	Package_SO:SOIC-8_3.9x4.9mm_P1.27mm	U2
1	LiPo JST-PH (discharge only)	Connector_JST:JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal	J3
1	PMOD JA	Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical	J1
1	SCL	TestPoint:TestPoint_Pad_D1.5mm	TP3
1	SDA	TestPoint:TestPoint_Pad_D1.5mm	TP4
1	USB Micro-B	Connector_USB:USB_Micro-B_Molex_105017-0001	JUSB

Questions

How big is the Aegis imu carrier PCB?

It measures 80 × 50 mm and has 2 copper layers, 1.6 mm thick.

What parts does the Aegis imu carrier use?

27 parts, built around the INA219AID, AP2112K-3.3, M2.5 and SS14. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the Aegis imu carrier KiCad files?

From the krishharma/aegis-mtstdp repository on GitHub, at the commit this page was made from: the board is pcb/aegis_imu_carrier.kicad_pcb and its schematic pcb/aegis_imu_carrier.kicad_sch. PCBKit opens the board in the browser, with nothing to install.

Can I use the Aegis imu carrier design in my own project?

Its repository states no licence, so its author keeps all rights: ask krishharma before reusing the design.

Category and platform

FPGA and programmable logic Sensors and measurement FPGA and CPLD

Topics

continual-learning fpga kicad neuromorphic python stdp verilog

Project files

Show this board on your page

A live frame, for any web page

<iframe src="https://pcbkit.io/embed/boards/krishharma-aegis-mtstdp" title="Aegis imu carrier in PCBKit" width="100%" height="480" style="border:0;border-radius:12px" allow="fullscreen" loading="lazy"></iframe>

A picture

<img src="https://pcbkit.io/embed/boards/krishharma-aegis-mtstdp.jpg" alt="Aegis imu carrier" width="1200" height="900">

A picture that opens the board, for a README

[![Aegis imu carrier](https://pcbkit.io/embed/boards/krishharma-aegis-mtstdp.jpg?size=s)](https://pcbkit.io/boards/krishharma-aegis-mtstdp)

Source

Repository: krishharma/aegis-mtstdp
Board file: pcb/aegis_imu_carrier.kicad_pcb
Commit: f50d327
Homepage: krishharma.github.io/aegis-mtstdp
Licence: Not stated

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