Smc power

Power board

Rev A — single-motor bench prototype power board. Feeds the driver board (48 V), the stepper motor brake (24 V) and the logic (5 V / 3V3).

Blocks

Design calculations: docs/power-design-notes.md

Connectors

Board-to-board by cables (no stacking / backplane).

Main-board side: 1 kΩ series resistor at the MCU ADC pin for VBUS_SENSE; one pull-up for FLT# (open-drain, active-low).

Stackup

4 layers, 1.6 mm, JLCPCB.

48 V, 24 V and SW nodes are routed on the 2 oz outer layers only (inner 1 oz layers can't carry or dissipate that current). Vias between L1 and L4 are fine — current flows in the plated barrel.

Order note: JLC's inner-layer default is 0.5 oz — select 1 oz explicitly.

Net classes

Values sized with IPC-2221 for 2 oz outer copper, ΔT ≈ 20 °C. Empty cells inherit Default.

FB nets (FB_24V, FB_5V) stay in Default on purpose — see layout notes below.

Why 0.6 mm: IPC-2221 B2 (external, uncoated, 31–100 V). Between two classes KiCad applies the larger clearance, so every net next to 48 V automatically gets 0.6 mm.

Rules of thumb:

• ~1 A per 0.3 mm via → parallel vias on high-current transitions.
• Track width is the default, not a limit — widen freely, never go narrower.

Layout notes

• FB: no net class needed — tiny current, width doesn't matter. What matters is placement: divider resistors right at the FB pin, short trace, never under or next to the SW node. A noisy FB makes the regulator output jitter.

Global constraints (Board Setup → Constraints)

Custom DRC rule (Board Setup → Custom Rules)

(version 1)
(rule "High-power nets: outer 2 oz layers only"
  (layer inner)
  (condition "A.NetClass == 'PWR_48V' || A.NetClass == 'PWR_24V' || A.NetClass == 'SW_NODE'")
  (constraint disallow track zone))

Tracking

Issues: label power · Project: https://github.com/users/efebasol/projects/12