4 layers60 × 28 mm
Boards by Misaka0x2730
14 boardsOpen-source boards designed in KiCad by Misaka0x2730 on GitHub, from 6 repositories. A board’s address here is its repository’s there.
- 4 layers53 × 42 mm
MioLink
Misaka0x2730/MioLink
ARM JTAG/SWD debugger (BlackMagic port) based on RP2040.
117 parts30GPL-3.0 - 4 layers94.3 × 81.8 mm
YukaLink revA
Misaka0x2730/YukaLink
Dual targets USB+ETH ARM JTAG/SWD debugger (BlackMagic port) based on RP2350. JTAG and SWD interfaces are implemented on PIO.
321 parts3GPL-3.0 - 2 layers87.3 × 53.3 mm
- 4 layers95 × 60 mm
- 2 layers61 × 34.3 mm
WeAct MSPM0G3507 CoreBoardAdapter
Misaka0x2730/MioLink_TestBench
A hardware-in-the-loop bench for automated testing of the MioLink debug probe.
5 parts1 - 2 layers42 × 35 mm
- 4 layers53 × 42 mm
MioLink
Misaka0x2730/MioLink
ARM JTAG/SWD debugger (BlackMagic port) based on RP2040.
112 parts30GPL-3.0 - 2 layers50 × 50 mm
MioLink adapter
Misaka0x2730/MioLink
ARM JTAG/SWD debugger (BlackMagic port) based on RP2040.
13 parts30GPL-3.0 - 4 layers53 × 54 mm
MioLink Pico
Misaka0x2730/MioLink
ARM JTAG/SWD debugger (BlackMagic port) based on RP2040.
73 parts30GPL-3.0 - 4 layers95 × 60 mm
- 2 layers65.6 × 34.3 mm
WeAct STM32F4x1CoreBoard Adapter
Misaka0x2730/MioLink_TestBench
A hardware-in-the-loop bench for automated testing of the MioLink debug probe.
5 parts1 - 2 layers65.6 × 34.3 mm
WeAct STM32F103 CoreBoard Adapter
Misaka0x2730/MioLink_TestBench
A hardware-in-the-loop bench for automated testing of the MioLink debug probe.
5 parts1 - 2 layers38.3 × 34.3 mm
WeAct STM32G0xxC0xxCoreBoard Adapter
Misaka0x2730/MioLink_TestBench
A hardware-in-the-loop bench for automated testing of the MioLink debug probe.
5 parts1