Boards using the 74LVC573AD

10 boards

Boards in 6 GitHub repositories, designed in KiCad, that use the 74LVC573AD by Nexperia (-40℃~+125℃ 1.4ns 1.65V~3.6V 1.7ns 3.4ns 74LVC 8 D Latch Tri-State SOIC-20-300mil Latches ROHS). See how each wires it, with its parts, size, README and files; the 74LVC573AD’s symbol, footprint and pinout are on its own page.

4 layers223.3 × 120.1 mm
ISA FPGA v2
robfinch/Cores
Cores ===== RTF's Cores Use at your own risk. Welcome to my galaxy of cores. Contained in the directories are IP cores, source code for digital circuits.
132 parts78
6 layers63.2 × 82.3 mm
SuperSamFPGA
jimbro1000/SuperSamFPGA
SamX8 design expanded to leverage basic FPGA instead of CPLD
105 parts
2 layers
ISA FPGA
robfinch/Cores
Cores ===== RTF's Cores Use at your own risk. Welcome to my galaxy of cores. Contained in the directories are IP cores, source code for digital circuits.
106 parts78
4 layers223.3 × 120.1 mm
ISA FPGA v2
robfinch/Cores
Cores ===== RTF's Cores Use at your own risk. Welcome to my galaxy of cores. Contained in the directories are IP cores, source code for digital circuits.
105 parts78
2 layers160 × 114.3 mm
VGAGAL
flypie/Ace-2019
Reimplimentation of the Jupiter ACE with slightly more modern hardware. https://www.jupiter-ace.co.uk/ the KiCad versions are the up to date designs which are available at https://jupiterdeuce.blogspot.com and…
77 parts13GPL-3.0
2 layers254 × 134.6 mm
S100 80386 SRAM V6
CatspersCoffee/S100-Boards
S-100 bus boards designed and built: Z80 and 80386 CPU cards, SRAM/DRAM memory, CPLD/FPGA I/O and SPI boards, an 18-slot backplane and bus terminator.
98 parts
2 layers254 × 134.6 mm
S100 Z80 V5
CatspersCoffee/S100-Boards
S-100 bus boards designed and built: Z80 and 80386 CPU cards, SRAM/DRAM memory, CPLD/FPGA I/O and SPI boards, an 18-slot backplane and bus terminator.
139 parts
4 layers224 × 120.1 mm
ISA65816
kitspace-test-repos/kicad6-file-collection

69 partsMIT
4 layers133.5 × 68.8 mm
Zx50 FrontPanelCard
mmosko/Zx50
This is the primary CPU board for the Zx50 8-slot passive backplane system. It hosts the Z80 microprocessor (running at 5 MHz to 10 MHz) and acts as the master controller for the primary bus.
23 parts
4 layers133.5 × 68.8 mm
Zx50 FrontPanelCard
mmosko/Zx50
This is the primary CPU board for the Zx50 8-slot passive backplane system. It hosts the Z80 microprocessor (running at 5 MHz to 10 MHz) and acts as the master controller for the primary bus.
22 parts