2 layers
2 layers34 × 25.5 mm
Nicklink
NickStassen/nicklinkNickLink v1.3 — compact STM32F103C8 breakout board (KiCad)
- Size
- 34 × 25.5 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 46
- Nets
- 55
- Pads
- 215
- Tracks, vias
- 730, 79
- Pours
- 5
- Routed
- Yes
- KiCad
- KiCad 10.0 (file 20260206)
- Created
- 10 Sep 2026
- Updated
- 14 Oct 2026
Overview
Nicklink is an open-source printed circuit board by NickStassen, from the NickStassen/nicklink repository on GitHub, published under the MIT licence. It is a 2-layer board of 34 × 25.5 mm with 46 parts on 55 nets, routed with 730 tracks and 79 vias.
It is built around the STM32F103C8T6, LSM6DSV and TLV76733DRVR, with the USBLC6-2P6, 1N5819WS and DMP2165UW among its other parts. Its parts include 14 capacitors, 12 resistors, 4 ICs, 3 diodes and 3 connectors. It belongs with the interfaces and adapters and microcontroller boards boards and the STM32 boards of this library.
Main components
6
STM32F103C8T6
LQFP-48(7x7)-40℃~+85℃ 12bit 20KB 2V~3.6V 32 Bit 37 64KB 72MHz ARM Cortex-M3 Built-in FLASH LQFP-48(7x7) Microcontrollers (MCU/MPU/SOC) ROHSSTMicroelectronicsMicrocontrollers (MCU/MPU/SOC)
LSM6DSV
LGA-14(2.5x3)-40℃~+85℃ 1.71V~3.6V 16bit 4.5KB Accelerometer Gyroscope SPI、I2C、I3C X,Y,Z X,Y,Z ±16g ±4000dps LGA-14(2.5x3) Accelerometers ROHSSTMicroelectronicsAccelerometers
TLV76733DRVR
WSON-6(2x2)-40℃~+125℃@(Tj) 1 1.4V@(1A) 16V 1A 3.3V 46dB@(1MHz) 50uA 60uVrms Fixed Over Current Protection、Over Temperature Protection、Soft Start Positive WSON-6(2x2) Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHSTexas InstrumentsVoltage Regulators - Linear, Low Drop Out (LDO) Regulators
USBLC6-2P6
SOT-666-6-40℃~+125℃ 150nA 17V 2 3.5pF 5.25V 5A@8/20us 6V ESD IEC 61000-4-2 Unidirectional SOT-666-6 ESD and Surge Protection (TVS/ESD) ROHSSTMicroelectronicsESD And Surge Protection (TVS/ESD)
1N5819WS
SOD-3231 Independent 1A 25A 40V 500uA@40V 600mV@1A SOD-323 Schottky Diodes ROHSGuangdong HottechSchottky Diodes
DMP2165UW
SOT-323-55℃~+150℃ 1 P-Channel 180mΩ@1.8V 1V 2.5A 20V 3.5nC@4.5V 32pF 335pF 700mW 72pF P-Channel SOT-323 MOSFETs ROHSDiodes IncorporatedMOSFETs
README
tools/README.mdNickLink build tools
NickLink is generated, not hand-edited. Change the inputs below, then rebuild. Everything runs in the kicad/kicad:10.0 Docker image, so no local KiCad install is needed. Freerouting runs in eclipse-temurin:25-jre.
Inputs
| File | What it holds |
|---|---|
spec.py | Parts, values, footprints, pin→net map, header pinout, LCSC numbers. Single source of truth. |
placement.py | Board size, label-strip geometry, every part's position/rotation, front part labels. |
board_template.kicad_pcb | Board setup only (stackup, solder-mask web, plot settings) for build_pcb.py. |
gen_sch.py | Schematic layout (block positions in its LAYOUT table). |
Pipeline
tools/build_all.sh # sch -> place -> autoroute -> stitch -> DRC -> nicklink.kicad_pcb
tools/fab.sh # gerbers, drills, BOM/CPL, PDFs, renders, checks/| Script | Step |
|---|---|
sch.sh | Runs gen_sch.py, ERC (must be 0/0), exports the netlist and checks it against spec.py (check_netlist.py); refreshes docs/schematic.pdf and docs/images/schematic.png. |
place.sh | Runs build_pcb.py: footprints, nets and symbol links from the netlist, outline, GND pours, silkscreen (front pin labels, back cheat sheet). Also writes _work/placed.png, a placement preview with courtyard-overlap check and ratsnest length (preview.py). |
autoroute.sh | Exports a Specctra DSN, runs Freerouting headless, imports the SES and refills the pours. Existing tracks are kept as fixed. With RIPUP=1, only locked pre-routes stay fixed, so a second pass may rip up and redo the first pass's tracks. |
stitch.py | Adds GND stitching vias wherever both pours have room, then drops any via that ends up on isolated copper. |
drc.sh | kicad-cli pcb drc with schematic parity; exits nonzero on any violation. JLCPCB limits come from the board setup plus nicklink.kicad_dru. |
route_try.sh | One placement variant end to end (place, route, stitch, DRC) for the seed search. |
render.sh | 3D top/bottom renders plus 2D layer plots (svg2png.py). |
compare.py | Any number of boards side by side at a fixed physical scale (px/mm), e.g. docs/images/compare-v1.1-v1.2-v1.3.png. Outline-only entries are allowed for boards without files. |
pinout.py | Writes docs/pinout.csv from spec.py and prints the README pinout table. |
netreport.py | Per-net length per layer and via count (check USB/HSE routing). |
build_pcb.py --resilk | Redraws only the silkscreen on an already-routed board. Use it for label tweaks without re-routing. |
fixroute.sh | Finishes a connection Freerouting left open: a small two-layer grid router (fixroute.py) joins the copper cluster holding one pad to the cluster holding another, e.g. tools/fixroute.sh in.kicad_pcb out.kicad_pcb GND R5.1 U1.23 0.25. Run drc.sh afterwards. |
gndnet.py | GND connectivity per pour island (KiCad treats a whole zone as one item), so floating island pairs show up. stitch.py uses the same idea. |
swapfp.py | Swaps a placed footprint for a same-pad variant (e.g. NoSilk) on a routed board, keeping nets and the symbol link. |
bringup_img.sh | Renders the board and draws the bring-up pictures (docs/images/bringup-*.png: ST-Link wiring, check points) from the real pad positions (bringup_img.py). |
nosilk.py | Copies a library footprint into nicklink.pretty without its silkscreen. |
kdock | Runs a command in the KiCad container with the repo and 3D models mounted. |
_work/, 3dmodels/ and the Freerouting jar are local caches, ignored by git. get3d.sh and autoroute.sh download them on first use.
Routing notes
placement.pyPREROUTEholds locked tracks laid before autorouting (currently the crystal nets), so the critical nets don't depend on Freerouting.- Freerouting's result is very sensitive to placement. If a placement change leaves nets unrouted, run a few
tools/route_try.sh s<n> "" <n>in parallel (at most about 4, since each Freerouting JVM needs a few GB of RAM). Each one nudges small parts by up to ±0.1 mm (NICKLINK_SEED), then routes, stitches and runs DRC. Bake the offsets of a clean seed intoPLACE. The current layout uses seed 3 (second review wave), which Freerouting routes fully on its own. If a seed leaves one or two items,fixroute.shis usually faster than more seeds. Hand-routed nets live inPREROUTE,PREROUTE_BandPREVIAS: crystal, IMU fan-out and GND returns, the power path, the USB-C orientation ties, and GND vias for boxed-in pads. build_all.shretries the route, stitch and DRC step (TRIES, default 3) because Freerouting's optimizer is time-limited.
Typical edits
- Swap a part or value: edit
spec.py, runbuild_all.sh. - Change only silkscreen text or labels: edit
build_pcb.py/placement.py, then runtools/kdock python3 tools/build_pcb.py --resilk nicklink.kicad_pcbandtools/drc.sh nicklink.kicad_pcb. - Move a part: edit
placement.py, runplace.shand look at_work/placed.pnguntil there are no overlaps, then runbuild_all.sh. - Change the header pinout: edit the
J1/J3maps inspec.py. Labels, the schematic,pinout.csvand the routing all follow. Runpinout.pyand update the README table.
Parts
46| Qty | Value | Footprint | References |
|---|---|---|---|
| 8 | 100n | Capacitor_SMD:C_0402_1005Metric | C1, C2, C3, C6, C9, C13, C14, C15 |
| 2 | 10k | Resistor_SMD:R_0402_1005Metric | R1, R10 |
| 2 | 15p | Capacitor_SMD:C_0402_1005Metric | C10, C11 |
| 2 | 1u | Capacitor_SMD:C_0402_1005Metric | C7, C8 |
| 2 | 4k7 | Resistor_SMD:R_0402_1005Metric | R7, R9 |
| 2 | Conn_02x10_Odd_Even | nicklink:PinHeader_2x10_P2.54mm_Vertical_NoSilk | J1, J3 |
| 1 | 0.5A | Fuse:Fuse_0805_2012Metric | F1 |
| 1 | 10k | nicklink:R_0402_1005Metric_NoSilk | R8 |
| 1 | 120R@100MHz | Inductor_SMD:L_0402_1005Metric | FB1 |
| 1 | 1N5819WS | Diode_SMD:D_SOD-323 | D2 |
| 1 | 1R | Resistor_SMD:R_0805_2012Metric | R12 |
| 1 | 1k5 | Resistor_SMD:R_0402_1005Metric | R3 |
| 1 | 2k2 | Resistor_SMD:R_0402_1005Metric | R2 |
| 1 | 330 | Resistor_SMD:R_0402_1005Metric | R6 |
| 1 | 4k7 | nicklink:R_0402_1005Metric_NoSilk | R11 |
| 1 | 4u7 | Capacitor_SMD:C_0402_1005Metric | C4 |
| 1 | 4u7 16V | Capacitor_SMD:C_0402_1005Metric | C12 |
| 1 | 5k1 | nicklink:R_0402_1005Metric_NoSilk | R5 |
| 1 | 5k1 | Resistor_SMD:R_0402_1005Metric | R4 |
| 1 | 8MHz | Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm | Y1 |
| 1 | BOOT0 | nicklink:SW_SPST_B3U-1000P_NoSilk | SW2 |
| 1 | DMP2165UW | nicklink:SOT-323_SC-70_NoSilk | Q1 |
| 1 | GREEN | LED_SMD:LED_0402_1005Metric | D3 |
| 1 | H1 | MountingHole:MountingHole_2.2mm_M2_ISO7380 | H1 |
| 1 | H2 | MountingHole:MountingHole_2.2mm_M2_ISO7380 | H2 |
| 1 | H3 | MountingHole:MountingHole_2.2mm_M2_ISO7380 | H3 |
| 1 | H4 | MountingHole:MountingHole_2.2mm_M2_ISO7380 | H4 |
| 1 | LSM6DSV | nicklink:LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y_NoSilk | U4 |
| 1 | RED | LED_SMD:LED_0402_1005Metric | D1 |
| 1 | RESET | nicklink:SW_SPST_B3U-1000P_NoSilk | SW1 |
| 1 | STM32F103C8T6 | Package_QFP:LQFP-48_7x7mm_P0.5mm | U1 |
| 1 | TLV76733DRVR | nicklink:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias03 | U2 |
| 1 | USBLC6-2P6 | Package_TO_SOT_SMD:SOT-666 | U3 |
| 1 | USB_C_Receptacle_USB2.0_16P | nicklink:USB_C_Receptacle_GCT_USB4085_EdgeSilk | J2 |
Questions
How big is the Nicklink PCB?
It measures 34 × 25.5 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Nicklink use?
46 parts, built around the STM32F103C8T6, LSM6DSV, TLV76733DRVR and USBLC6-2P6. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Nicklink KiCad files?
From the NickStassen/nicklink repository on GitHub, at the commit this page was made from: the board is nicklink.kicad_pcb and its schematic nicklink.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the Nicklink design in my own project?
Its repository publishes it under the MIT licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).
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