
Device
jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack
Device is an open-source printed circuit board by jayis1, from the jayis1/hardware-design-lab repository on GitHub. It is a 4-layer board of 120 × 80 mm with 11 parts on 52 nets, routed with 6 tracks and 3 vias.
It is built around the STM32H7A3VIT6, BMP390 and SDP810-500PA. Its parts include 6 ICs, 2 diodes and 2 connectors. It belongs with the ESP32, STM32 and RISC-V boards of this library.
Author: jayis1
Full-cycle, open-source hardware device designs — from concept to KiCad schematics to production firmware to companion mobile apps. Every device is fully open: schematics, board layouts, C/Python firmware, and React Native apps. Each device lives in its own subfolder with complete deliverables.
Every device folder contains the full stack — not just docs, but real buildable artifacts:
| Category | Files | Description |
|---|---|---|
| Engineering Docs | phase1_conceptual_architecture.md → phase4_software_stack.md | 4-phase design process: requirements, BOM & netlists, PCB layout rules, software stack |
| KiCad Schematics | kicad/*.kicad_pro, *.kicad_sch, *.kicad_pcb | Full schematic with real component symbols, net labels, power flags, and board outline with placed footprints |
| C/Python Firmware | firmware/main.c, registers.h, board.h, drivers/, Makefile | Production-quality MCU firmware — init code, drivers with DMA, USB descriptors, wire protocol |
| React Native App | app/App.js, screens/, components/, utils/protocol.js, package.json | Companion mobile app for device control, configuration, and status display |
Every device follows the same rigorous 4-phase process:
| Phase | Document | Contents |
|---|---|---|
| Phase 1 | phase1_conceptual_architecture.md | Purpose, performance targets, constraints, block diagram, bus topology, power domains |
| Phase 2 | phase2_component_selection_schematics.md | BOM with real part numbers, pinouts/MUX tables, decoupling networks, netlists, impedance matching |
| Phase 3 | phase3_pcb_blueprints_layout.md | PCB stackup, routing rules, length matching, via strategy, thermal management, DFM notes |
| Phase 4 | phase4_software_stack.md | MMIO/register defs, clock & GPIO init (production C), critical device driver, device tree, bootloader |
| # | Device | Status | Description |
|---|---|---|---|
| 1 | eag-7000/ — Edge AI Gateway | ✅ Docs complete, KiCad/firmware/app pending | i.MX8MP + Hailo-8 NPU, 30 TOPS, fanless industrial, 2×2.5GbE, CAN-FD |
| 2 | chronos-rtk/ — Dual-Frequency RTK GNSS Receiver | ✅ Complete | ZED-F9P + STM32L4 + LoRa mesh, cm-level positioning, 868/915 MHz ISM |
| 3 | vortex-sdr/ — Portable SDR Spectrum Analyzer | ✅ Complete | STM32H743 + iCE40UP5K FPGA + ADF4351 PLL, 100kHz–6GHz, dual-FFT waterfall |
| 4 | web-slack-ledger/ — WebSlack Ledger | Build-tested prototype; physical validation pending | Two-encoder differential travel and reversal ledger for slow hand-fed strip fixtures |
| 5 | slip-window/ — Slip Window | Build-tested prototype; physical validation pending | Slip-casting cradle residence, interrupted draining, longest drain segment, and mold-opening notebook |
| 6 | stencil-orbit/ — Stencil Orbit | Build-tested prototype; physical validation pending | Manual screen-printing carousel station index, registration continuity and per-station tool-use notebook |
| 7 | crossover-track/ — Crossover Track | Build-tested prototype; physical validation pending | Four-contact cart trial recorder and guided ABBA lane-swap comparison separating cart and lane time contrasts |
| 8 | takeup-atlas/ — Takeup Atlas | Build-tested prototype; physical validation pending | Two-shaft reversal trials recording first output response, three-edge confirmation and rejected attempts in hand-operated mechanisms |
| 9 | chord-window/ — Chord Window | Build-tested prototype; physical validation pending | Four-switch chord press spread, shared hold and release timing before keyboard filtering, with local policy comparison |
| 10 | detent-loop/ — Detent Loop | Build-tested prototype; physical calibration pending | Hand-operated sliding-catch force–travel loops with explicit zero, turnaround, signed work and local evidence export |
| 11 | tilt-break/ — Tilt Break | Build-tested prototype; physical calibration pending | Manual incline home-departure resistance brackets and independently qualified downstream puck arrival |
| 12 | pipette-path/ — Pipette Path | Build-tested prototype; physical training validation pending | Two-stop manual pipette plunger sequence recorder with operator-declared source immersion; not a volume calibrator |
| 13 | flow-pause/ — Flow Pause | Build-tested prototype; physical validation pending | Declared-supply hopper discharge silence, intervention precedence and recovery notebook; not a blockage detector |
| 14 | sieve-shuttle/ — Sieve Shuttle | Build-tested prototype; physical validation pending | Four-zone manual sieving motion matrix, opposite-axis traversals, same-zone returns and longest directional runs; not separation efficiency |
| 15 | bellows-phase/ — Bellows Phase | Build-tested prototype; physical validation pending | Direction-conditioned inlet/outlet flap-position intervals across manual bellows strokes; not airflow or efficiency |
| 16 | shutter-quartet/ — Shutter Quartet | Build-tested prototype; optical validation pending | Four-point fragmented exposure, missing-point and reopening notebook for slow hand-operated teaching shutters; not camera calibration |
| 17 | coupon-transit/ — Coupon Transit | Build-tested prototype; physical validation pending | Two-holder rack-to-rack transfer durations, same-rack returns and interrupted-observation notebook; not specimen identity or treatment verification |
| 18 | pattern-sled/ — Pattern Sled | Build-tested prototype; physical validation pending | Three-track mechanical program-strip repeat comparator with a learned sixteen-word reference, per-position mismatches and terminal alignment-loss diagnostics |
| 19 | kit-multiset/ — Kit Multiset | Build-tested prototype; physical validation pending | Tray-delimited unordered 2:1:1 bin-paddle recipe declarations, conservative abandonment and local evidence export; not inspected part quantities |
| 20 | shim-bracket/ — Shim Bracket | Build-tested prototype; physical validation pending | Indexed feeler-gauge fit/refusal declarations with persistent monotonicity contradictions; not calibrated gap measurement |
| 21 | catch-witness/ — Catch Witness | Build-tested prototype; physical validation pending | Settled-latch reopening notebook with expiring handle/tug associations and separate unseated, unexplained and aborted outcomes; not a retention-force gauge |
| 22 | beat-aperture/ — Beat Aperture | Build-tested prototype; physical validation pending | Two-pendulum return apertures retaining zero, single and multiple comparison returns within each reference cycle; not continuous phase measurement |
| 23 | grip-lattice/ — Grip Lattice | Build-tested prototype; physical validation pending | Footswitch-delimited three-zone dummy-handle contact combinations, segment lengths and explicit unknown intervals; not a force or ergonomic assessment instrument |
A high-performance, fanless industrial Edge AI Gateway for real-time ML inference at the network edge.
| Parameter | Value |
|---|---|
| AI Throughput | ≥30 TOPS INT8 (2.3 TOPS SoC + 26 TOPS Hailo-8) |
| CPU | NXP i.MX8M Plus — 2× Cortex-A72 @ 2.0 GHz + 1× Cortex-M4F @ 800 MHz |
| Memory | 2× Micron MT53D512M32D4DS — 8GB LPDDR4X @ 4267 MT/s |
| Storage | 32GB eMMC 5.1 (boot) + 128GB NVMe M.2 2242 (data) |
| Networking | 2× 2.5GbE (AQR111C) + 1× 5GbE USB-C |
| Industrial IO | 2× CAN-FD, 3× SPI, 4× I2C, 5× UART, 1× MIPI-CSI2 |
| Power | 12V DC / PoE+ (802.3at), ≤15W typical, 25W peak |
| Form Factor | 100mm × 72mm × 25mm, DIN-rail mountable |
| Operating Temp | -40°C to +85°C (industrial) |
A portable, handheld spectrum analyzer covering 100 kHz to 6 GHz with dual-channel FFT, real-time waterfall display, capacitive touchscreen, and BLE companion app. Designed for RF engineers, ham radio operators, and EMC compliance testing.
| Parameter | Value |
|---|---|
| Frequency Range | 100 kHz – 6 GHz (dual-conversion superheterodyne) |
| MCU | STM32H743ZIT6 — Cortex-M7 @ 480 MHz, 1MB Flash, 1MB RAM |
| FPGA | Lattice iCE40UP5K — FFT/waterfall acceleration |
| PLL Synthesizer | ADF4351 — 35 MHz to 4.4 GHz (6 GHz with ADF5002 prescaler) |
| ADC | AD9645 — 14-bit, 61.44 MSPS dual-channel |
| Display | ILI9341 — 2.8" 320×240 TFT with capacitive touch |
| BLE | nRF52840 — 2 Mbps BLE 5.0 companion link |
| Power | 3.7V LiPo (TPS62A02 buck + AMS1117 LDO), USB-C charging |
| Form Factor | 120mm × 75mm × 18mm, handheld |
| Operating Temp | -20°C to +55°C (commercial) |
| Component | License |
|---|---|
| Hardware design (KiCad) | CERN-OHL-S v2 |
| C firmware & drivers | GPL-2.0 |
| Python tools & scripts | MIT |
| React Native companion apps | MIT |
| Qty | Value | Footprint | References |
|---|---|---|---|
| 1 | 340nm_300mW | LED_SMD:LED_3528 | D2 |
| 1 | 650nm_50mW | OptoDevice:TO-18_3Pin | D1 |
| 1 | Anemometer_RS485 | Connector_JST:JST_PH_B4B-PH-K_1x04_P2.00mm_Vertical | J4 |
| 1 | BMP390 | Package_LGA:Bosch_LGA-10_2.5x2.5mm_P0.6mm | U5 |
| 1 | ESP32-C6-MINI-2U | RF_Module:ESP32-C6-MINI-2U | U2 |
| 1 | LTC2351-14 | Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm | U3 |
| 1 | SDP810-500Pa | Sensor:Sensirion_SDP8xx_DFN-8_5x8mm_P1.25mm | U6 |
| 1 | SHT45 | Sensor:Sensirion_DFN-4-1EP_1.5x1.5mm_P0.5mm | U4 |
| 1 | ST7789V_240x320 | Display:ST7789V_2.4in_FPC_10pin | DISP1 |
| 1 | STM32H7A3VIT6 | Package_BGA:UFBGA-176_10x10mm_P0.65mm | U1 |
| 1 | USB-C | Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12 | J1 |
It measures 120 × 80 mm and has 4 copper layers, 1.6 mm thick.
11 parts, built around the STM32H7A3VIT6, BMP390 and SDP810-500PA. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
From the jayis1/hardware-design-lab repository on GitHub, at the commit this page was made from: the board is aerocast/kicad/device.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.
Its repository states no licence, so its author keeps all rights: ask jayis1 before reusing the design.

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

jayis1/hardware-design-lab
Full-cycle hardware device designs — each device in its own subfolder with architecture, schematics, PCB layout, and software stack

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