AFE

2-Channel Digital Oscilloscope

Project Overview

Goal: Build a custom data acquisition system capable of capturing and displaying fast analog signals with at least a 15 MHz bandwidth.

Project Scope:

• Custom PCB & Analog Front-End (AFE): Designed and routed in KiCad.
• FPGA Data Acquisition Engine (DAQ): Written in VHDL, deployed on a Tang Nano 9K (Gowin GW1NR-9).
• MCU Control & Data Handling: Written in C (Arduino core) on a Raspberry Pi Pico, featuring a pseudo-SCPI command parser.
• PC Software: A basic Python GUI for data visualization.

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System Architecture

The system is divided into four main functional blocks:

1. Analog Front-End: Conditions the input signal by applying attenuation/amplification, removing or shifting the DC offset, and applying AC/DC coupling.
2. Digitization: An ADC converts the conditioned analog signal into the digital domain. Currently, a crystal oscillator and a clock buffer/splitter IC provide the clock to both the ADC and the FPGA.
3. FPGA DAQ: Manages the high-speed digital logic, executing pre-filling, edge triggering, post-filling, and hardware-level memory buffering.
4. MCU & PC Software: A microcontroller asynchronously reads the buffered data from the FPGA (two channels simultaneously via a custom parallel protocol). It then transmits this data to a PC for visualization while receiving SCPI commands to control the FPGA (horizontal scaling) and the AFE (vertical scaling).

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Hardware Details

The Analog Front-End (AFE)

The AFE is a fully custom design inspired by commercial oscilloscope teardowns and open-source projects. The signal chain operates as follows:

• Input Stage: The signal enters via a BNC connector, passes through an AC/DC coupling circuit, and reaches a relay that toggles between 1:1 and 10:1 attenuation.
• Protection & Buffering: A BAV99 diode provides input protection before the signal hits an ADA4817 FET-input op-amp acting as a buffer.
• Offset & Gain: The signal is routed to an AD8132 Fully Differential Amplifier (FDA), where the DC offset is applied. Finally, it is amplified by an AD8330 Variable Gain Amplifier (VGA), which also acts as the driver for the AD9288 100MSPS ADC.

The Offset Circuitry

The offset adjustment is achieved by injecting a control voltage into one of the FDA pins. This voltage is generated by an MCP4728 quad-channel DAC, which simultaneously controls the VGA gain. By utilizing a summing amplifier connected to the negative rail, the offset voltage can swing approximately ±4.5V.

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Digital & Firmware

The FPGA Engine (VHDL)

The core of the DAQ engine is a state machine responsible for the pre-fill, trigger, and post-fill capture sequence. The VHDL architecture includes several key design features:

• Clock Domain Crossing: Buffer memory is implemented using Gowin Semi Dual Port RAM IP cores. To safely cross from the high-frequency ADC clock domain to the slower MCU read clock domain, the state machine halts capture and enters a STOP state, preventing concurrent memory overwrites while the MCU reads the data.
• Hardware Data Unwrapping: Instead of forcing the slower MCU to track indices and unwrap a circular buffer, the FPGA handles this natively. The logic automatically aligns the data so the trigger source sample is always properly positioned (e.g., in the exact middle for a 50/50 prefill/postfill ratio). The MCU simply reads and transmits raw, glued data for both channels.
• Command Interface: An SPI read block receives and parses commands sent by the MCU.

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Results & Verification

Testing was conducted in progressive stages to isolate the scope of potential problems:

1. Digital Simulation: The first round of testing was performed by feeding simulated digital data from a Raspberry Pi Pico into the FPGA. The logic was verified using the GoWin Analyzer Oscilloscope app.

2. ADC Verification: A real 1 MHz sinusoidal signal was then sampled by the ADC to confirm analog-to-digital conversion integrity.

3. Full System Test: A PyQt5 visualization application was used to interface with the hardware. Final testing confirmed that the front-end analog bandwidth reaches approximately 19 MHz, successfully exceeding the 15 MHz project goal.

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Future Improvements

While the current revision meets all initial project goals, several architectural improvements could be made in future iterations:

• Simplify the AFE: The FDA is not strictly necessary; the front-end could be streamlined by merging the offset functionality directly into the VGA.
• Improve Offset Stability: The offset section could be reworked to utilize a dedicated, high-stability voltage reference rather than relying on the main power rail.
• Upgrade the VGA: The analog VGA could be swapped for a digitally controlled alternative, such as the LMH6518 or AD8370, for more precise gain stepping.
• Adjust Clock Architecture: Instead of using an external crystal to clock the ADC and decimating samples on the FPGA to change the timebase, the FPGA could generate and drive the ADC clock directly, allowing for dynamic sampling rate adjustments. The PCB was designed with such a possibility in mind so it just needs necessary VHDL code and one jumper changeover.
• Revise the PSU: Currently, the project is powered by a custom charge-pump-based PSU that introduces significant noise. While small-signal/high-gain performance analysis was outside the initial scope, it is likely hampered by this setup.
• System Integration: Replacing the Tang Nano 9K development board with a discrete FPGA integrated directly onto the PCB could improve digital signal integrity, which is theorized to be the cause of some signal glitches observed during testing.
• MCU Migration: Transitioning from the Raspberry Pi Pico dev board to an integrated STM32 chip on the PCB would streamline the design and eliminate the reliance on the RP2040's external flash memory dependencies.
• Increase Memory Depth: The Gowin FPGA has limited BRAM, restricting the buffer memory size. This could be addressed by upgrading to a larger FPGA (e.g., the 20 series) or adding discrete RAM. Using a module like the Primer 20K (which features a SODIMM connector and onboard RAM) could bypass the complexities of routing high-speed memory interconnects on a custom PCB. Additionally, sourcing bare Gowin ICs can currently be challenging.
• Interleaved Mode: Inspired by other open-source projects like ScopeFun, interleaving could effectively double the sampling rate. Bridging the signal from one channel to the other and forcing sampling 180 degrees out of phase is highly feasible thanks to the AD9288's two independent clock inputs.

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Expansion Potential

Currently, the project has reached a successful proof-of-concept stage and sits at a crossroads. For simplicity, the captured data is currently sent to a PC app and visually represented as raw sample values. For the next version, there are two primary paths forward:

1. PC-Attached Oscilloscope: Expand upon the PC app concept, turning it into a fully-featured interface with potential for robust data logging, advanced measurements, and network control.
2. Standalone Benchtop Device: Pivot into a self-contained benchtop instrument by swapping the MCU for a more powerful processor and integrating a dedicated hardware UI (an LCD screen, rotary encoders, and physical buttons).