2 layers30 × 60 mm

Vex Debug
RIT-VEX-U/VexDebugBoard_PCB
This is the main hardware repository for the V5 Debug Board: a board designed to slot into the VEX V5 Smart Port, and transmit debug data over a websocket to a laptop.
41 parts1GPL-3.0
Open-source boards designed in KiCad by RIT-VEX-U on GitHub, from 2 repositories. A board’s address here is its repository’s there.

RIT-VEX-U/VexDebugBoard_PCB
This is the main hardware repository for the V5 Debug Board: a board designed to slot into the VEX V5 Smart Port, and transmit debug data over a websocket to a laptop.

RIT-VEX-U/VexIfaceExpander
This project aims to create a board that breaks out a smart port to both Qwiic Connector (I2C) and Mikrobus, for additional expansion to the V5 ecosystem.