MonolithDev

Monolith dev board — KiCad project

Dev board for the Monolith battery bank, described in ../../docs/devboard/circuit-description.md. The schematic was first drawn on 2026-10-11 with the KiCad MCP.

This board was never ordered or built. On 2026-10-18 the dev board was skipped and production P0 was built directly. The live design is P0 in ../Production/ on the Production branch; the current spec is docs/spec.md. This folder is kept as the reviewed reference (rev A8) that P0 was derived from, and as history: everything below describes the dev board as it stood on 2026-10-17, not the current product. The cell assumed here (EVE INR21700-58E, used for the cell 3D model on the holder footprint) is superseded too: the pack uses the BAK N21700CX-65E (4S1P, 14.0 V nominal, 91 Wh); see docs/spec.md.

Still in use by P0, so don't delete or rename: hardware/Production/tools/make_production.py and make_board.py copy the schematic sheets, MonolithDev.kicad_sym, MonolithDev.pretty/, fp-lib-table, sym-lib-table, MonolithDev.kicad_pro, MonolithDev.kicad_dru and read MonolithDev.kicad_pcb from here; make_3d_models.py copies three STEP files from 3dmodels/; layout_production.py runs tools/move_region.py, tools/place_fields.py and tools/check_overlaps.py (which import tools/sch_geom.py); pack_bus_sims.py (and through it low_profile_sims.py) loads tools/cap_sims.py.

Status (rev A8, 2026-10-14; routed 2026-10-17):

• Schematic: four datasheet reviews done (../../docs/devboard/schematic-review-*.md), cost-down applied, review 4 fully applied (rev A8, items 41–42).
• Board: 6-layer, every part placed by block (tools/place_blocks.py), updated for rev A8; routed and DRC-clean on 2026-10-17 (item 49), fab outputs in fab/ (item 50). Not ordered, not built.

See Status for the checks and the costed BOM.

Files

Drawing conventions (cleanup pass, 2026-10-11): signal and power flow left to right, supplies up and ground down; each sheet is split into headed functional blocks with a NOTES block; rails use power symbols (PACK_P, 3V3, GND, and a separate ground-reference symbol for CELL_N, the gauge's VSS); short local connections are real wires, long runs use net labels; unused IC pins are tied with short bars to one symbol; MPNs live in properties, not the value text; every sheet has a filled title block. Readability pass (rev A2, following MacroFab's schematic guide): no text overlaps anywhere, values are the value or part number only (explanations live in each part's hidden Notes property and the sheet NOTES), direct same-page connections are wires rather than duplicate labels, sheet-pin names sit inside the sheet boxes, cap banks are at 10.16 mm pitch so every value reads horizontally, and the top sheet carries a revision log.

Wiring pass (rev A3): wires instead of labels wherever parts sit on the same block. Passives are placed on the row of the pin they serve (datasheet style): the BQ40Z50 cell-tap filters are an R/C ladder fanning into the VC pins; BAT/VCC/PBI/PACK/SMBus, the BQ25756 VAC divider, pull-down comb, bootstrap caps, FB divider and DRV_SUP, the TPS25751 I2Cc pull-ups (off a short LDO_3V3 rail), the STM32 BOOT0/NRST/SWD header and the TPS62177 PG pull-up are all drawn with wires. Labels remain for genuinely long runs and cross-sheet nets (I2C buses, gate drive to the FETs, cell taps from the holders, NTC dividers, test points). Local labels went from 275 to 198 and wires from 272 to 350. Nets that are fully wired lost their old names and now carry KiCad's automatic names (for example Net-(U101-VC1)).

Tools (most of tools/ is one-shot history: the finish_*, review4_*, mcu_cc2340.py, remove_tmp1075.py, downsize_passives.py, bom_fee_cut.py, gate_diodes.py / add_gate_diodes_board.py scripts each applied one numbered change below to the sheets or board of their day and won't re-run on the current files; the *.uuids files are the routers' re-run sidecars):

• tools/place_blocks.py places every footprint in its sheet's zone (current placement, rev A7). It changes footprint positions only; no copper or silkscreen.
• tools/reset_board.py net.sexp [REF,...] then reset_board.py x --load strips copper, silk text and zones, deletes footprints the schematic no longer has, and reloads footprints whose library footprint changed (or the listed refs) at their old positions.
• tools/bom_cost.py [boards] exports the netlist and prices it from JLC into bom_cost.csv.
• tools/make_footprints.py, tools/make_symbols.py, tools/make_3d_*.py generate the project footprints, symbols and 3D models.
• tools/place_parts.py, route_power.py, route_signals.py, fanout_gnd.py, autoroute.py: the rev A5 placement and routing scripts, written for the old parts. Kept for their silkscreen pass and routing methods; they need updating before they run on the current board.
• tools/setup_board.py writes the board outline, stack-up, mounting holes (only while the board is empty), JLC design rules, net classes and MonolithDev.kicad_dru.
• tools/netlist_to_board.py net.xml [REF,...] pushes a kicad-cli sch export netlist --format kicadxml netlist into the board: pad nets, symbol links, values and fields, and swaps footprints whose schematic footprint changed (listed refs are refreshed from the library). Use it instead of the KiCad MCP's sync_schematic_to_board, which mishandles the reused USB port sheet (it left port 1 unconnected and merged the two ports' nets). It doesn't add new footprints; use KiCad's Update PCB from Schematic (F8) for that, then check parity.
• tools/junctions.py sheet [--drop-labels A,B] adds missing junction dots (KiCad only joins a wire end to the middle of another wire if a junction is there, and some MCP move/rotate operations delete junctions) and optionally deletes labels by name. Run it on every sheet after any edit, then diff the netlist.
• tools/remove_items.py sheet spec.txt deletes specific wires/labels by coordinates.
• tools/route_labels.py auto-wires short label-only nets (A* on the 1.27 mm grid, never touching other nets). Its output was only kept where it read cleanly; the main wiring was laid out by hand.
• tools/check_overlaps.py [-v] reports every place where text, labels, symbol bodies, pin numbers or wires collide (text widths calibrated against KiCad's renderer). It should print TOTAL 0.
• tools/place_fields.py re-places Reference/Value text on all sheets into free space next to each part and re-orients labels about their anchors. Run it after moving parts, then run the checker.
• tools/tidy_fields.py wrote the title blocks (the older field placement in it is superseded by place_fields.py).

Cross-sheet signal nets use global labels (PACK_P, GND, 3V3, SDA, SCL, IRQ_N, EN_5V1/2, 3V3_SLEEP). Both ports share one sheet file, so any change to it applies to both ports.

Board (placed 2026-10-14; routed 2026-10-17, item 49)

• 196 × 115 mm (planned 175 × 115; see placement), 6 layers, 1.6 mm, 2 oz outer / 0.5 oz inner, ENIG, vias epoxy-filled and capped (2026-10-14; was 4 layers, 0.8 mm, 2 oz / 1 oz). The four holders need ~96 × 110 mm, so the spec's 100 × 80 mm grew; holders on the left, electronics on the right (floorplan below).
  • Why 6 layers: JLC quoted $88.20 against $119.90 for the 4-layer board at this size (5 boards). Via-in-pad filling (POFV) is free on 6+ layers, and the board gets two solid GND planes under the power stages.
  • Why 1.6 mm: your choice; it uses Shou Han's 1.6 mm version of the IP68 USB-C connector (same land pattern). Production thickness is still open: 0.8 mm was chosen to match production.
• Stack-up (approximate; set it to JLC's 6-layer 1.6 mm stack at order time). No impedance-controlled nets. High current stays on the 2 oz outer layers.

• Six M3 board-only mounting holes (H1–H6) at the corners and at x = 106 mm top and bottom, so the heavy holder block is supported at all four corners.
• J401/J501 are placed and locked on the right edge at y = 32 and 68 mm (from the top-left corner); the outline is broken there and each connector footprint draws its own 10.2 × 5.65 mm notch.
• Rules (JLC 6-layer, 2 oz outer): 0.15 mm track/gap, vias ≥ 0.3 mm drill with ≥ 0.45 mm pad (JLC's standard; smaller costs extra; presets 0.3/0.45, 0.3/0.6, 0.4/0.8), component-hole ring ≥ 0.25 mm, copper ≥ 0.25 mm from edges (0.2 mm at the USB-C notches, JLC's floor), legend ≥ 0.8 mm. Custom rules in MonolithDev.kicad_dru.
• Net classes: HighCurrent (2.5 mm: pack bus, cells, FET mid-point, VBAT_SYS, PPHV, VBUS, switch nodes, sense-resistor power sides), Power (0.8 mm: 5 V / 3.3 V rails), GND, GateDrive (0.4 mm), Default (0.2 mm).
• Netlist loaded: 416 footprints plus the 6 mounting holes; kicad-cli pcb drc --schematic-parity reports 0 parity issues.
• Layout reset for the next attempt (2026-10-14, tools/reset_board.py). The board now holds only the outline (Edge.Cuts), the mounting holes and the parts.
  • Removed: every track, via, zone (pours and the ANT_KEEPOUT rule area), board silkscreen text and group.
  • Synced to the schematic: 11 parts no longer in it were deleted (F101, D403/D503, R405–R408, R505–R508). 61 parts whose footprint changed were reloaded at their old positions (cost-down inductors, caps and FETs, U203, the solder jumpers, the test pads). The 75 parts added since the last placement sit in three rows below the outline (gauge, port 1, port 2): second-level protection, liquid detection, tuning parts, Q407/Q408 and their 5xx twins.
  • netlist_to_board.py then set nets and fields. kicad-cli pcb drc --schematic-parity reports 0 parity issues; the remaining DRC items are the unrouted nets and overlaps from the old placement.
  • Before placing:
    • Re-plan each power stage: two PDFN3333 FETs per leg, the 11.5 × 10 mm SMMS1040 inductor, and C430/C438 across each pair's high-side drain and low-side source. Q402's gate can now face the BQ25756.
    • Put F102 at the end of BT104's CELL_P_RAW strip with Q104 beside it, keeping it away from the FET heat (65 °C rating).
    • Re-add the antenna keep-out.
    • TPD2S300 escape → replaced by TPD4S201 (2026-10-14). The TPD2S300's centre ball B2 (GND) is boxed in by the other eight (0.17 mm between ball edges), so it needed a 0.15 mm via-in-pad, a costly JLC option. With the 6-layer board at JLC's standard 0.3 mm via, U405/U505 became TPD4S201 (VQFN-20, item 39), which escapes from its perimeter pads and exposed pad. History of the via-in-pad attempt:
      • The via: B2 in TI_YFF0009_DSBGA-9_P0.4mm is a plated 0.15 mm drill in a 0.25 mm pad (JLC's minimum via; 5:1 aspect ratio on the 0.8 mm board), down to the In1 GND plane, 0.16 mm from its neighbours. Top mask and paste are the same as the other balls.
      • Rules (removed with the swap): board-setup floors of 0.15 mm hole / 0.05 mm ring, with DRU rules keeping 0.2 mm / 0.1 mm elsewhere.
      • The eight outer balls escape straight out on F.Cu at the normal 0.15 mm rules.
  • place_parts.py, route_power.py, route_signals.py and fanout_gnd.py were written for the old placement and still need the new parts. Their .uuids sidecars point at deleted copper. The notes below describe that earlier placement.
• Block placement (rev A6, 2026-10-14, tools/place_blocks.py). Every part is on the board, one zone per schematic sheet: gauge column (x 104–134), MCU band along the top edge, one 36 mm port band per USB-C connector (port 2 is port 1 moved 36 mm down), sleep-current block along the bottom. No courtyard overlaps; DRC parity 0. Only footprint positions changed: no copper, and silkscreen is still the footprints' default reference text.
  • Gauge, MCU, sleep: kept their old positions. Added: the BQ294700 block (U102, tap filters, Q104 heater FET) beside F102 at the bottom of the gauge column, away from the FETs. C105 (now 1206) and the HT7550-1 LDO group were moved clear of their neighbours.
  • Port power stage, centred on the connector's line (y 32 / 68):
    • Order: output bank | Q402/Q408 | L401 | Q407/Q401 | input bank.
    • Each half-bridge is a vertical pair with both switch-node sides facing the inductor pad.
    • On the outer side the high-side drain sits over the low-side source, and the 0603 HF cap (C430 / C438) stands across that joint. Its pads are about 1.5 mm from the FET pins.
    • The 22u MLCCs continue the same row on the same two copper strips, with the polymer caps one step further out.
    • The gate resistors sit at each gate pin (LS-input and HS-output gates face the BQ25756). The DNP snubbers are under the bridges.
  • Port controllers: the BQ25756 sits above the inductor, turned so its gate-drive pins face the power stage. Its bootstrap / DRV_SUP / REGN parts form one row between them, the SRP/SRN/FB parts are on the output side, ACP/ACN/ACUV/FSW on the input side, and the programming resistors on top. The TPS25751 and EEPROM are to its right, the TPD4S201 and liquid detection in the corner above the connector.
  • Port buck and probes: the PP5V buck runs along the bottom of the band (input caps, IC, inductor, output caps, with the EN/SS/FB row under it). SW1/SW2/GND probe loops are under the inductor, with a 2 × 4 probe field for logic and rails and the I2CC header in the top-left corner.
  • Still to do: a silkscreen pass (reference text, test-point labels, block titles), then routing.
• Rev A7 board update (2026-10-14, item 40). reset_board.py deleted the 14 parts the schematic dropped (TH301–TH305, R303, R308–R311, R316, R320, TP305, TP306), reloaded U301 (CC2340R5MODA footprint) and C308–C312 (now 0402) at their old spots, and added U302–U306, C313–C315 and R321; netlist_to_board.py set the nets. place_blocks.py then placed them (MCU_LAYOUT, SENSOR_LAYOUT); nothing else moved. No courtyard overlaps; DRC parity 0.
  • U301: antenna (pin-1) end at the top edge, courtyard on the edge (module body 0.3 mm in, pads 0.6 mm in), x = 150 mm. The board edge either side is free of rule areas, so the GND planes run 46 mm to the right edge and the full width to the left (TI fig. 9-2 asks for A, B ≥ 10 mm, 20 mm for ~50 % efficiency). Parts on top in that strip (J302, J303, the match) are fine as long as the planes stay solid under them.
  • RF match in the corner left of pins 3/4: C313 (RFIO) and R321 (ANT_IN) in series, pads facing their pins, joined on the left, where C314 (DNP) shunts the node to GND. C315 stands on ANT_IN with its GND pad beside the module's GND pin 1. Every match pad is within 2 mm of its pin. Below it, one column by the 3V3 pins 6/7: C302, C303, C301, then R302/C304 for RSTN.
  • ANT_KEEPOUT dropped. The rev A5 rule area banned pours either side of the ST module's antenna. TI asks for the opposite: ground along the edge either side, and a no-copper area only under the antenna. The footprint carries that area (7.0 × 3.2 mm on the inner and bottom layers, 5.4 mm between the pads on F.Cu).
  • TMP1075s: the exposed pad (GND) sits on GND copper next to what each one measures, with its 0.1 µF at the V+ pin.
    • U302/U303 are under each output bank's PGND strip, beside Q408/Q508 (TH301/TH302's spot).
    • U304 is between D401 and the port 2 liquid-detection column, below TP402 (TH303's spot).
    • U305 (DNP) is under L401, between the SW1 and GND probe loops.
    • U306 (DNP) is between Q101 and Q102. C110/C111, the cap pair across the protection FETs, moved into the gap to its right, with CELL_P up toward Q101 and PACK_P down toward Q102. The FETs' drains are FET_MID, not GND, so U306 reads them through the board.
  • Sensor footprint: U302–U306 use MonolithDev:TI_DSG0008A_WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm_Vias0.3mm. KiCad's ..._ThermalVias version had 0.2 mm via drills, below this board's 0.3 mm minimum (10 DRC errors). The schematic field was changed and the parts were reloaded in place.
• History: the rev A5 placement (superseded by the block placement above).
• Placement (first pass, 2026-10-12): all 326 footprints placed by tools/place_parts.py; DRC clean apart from the unrouted connections. Board grew to 196 × 115 mm: the holder courtyards (94.7 mm) collided with corner holes, so the holder block moved right and the middle holes moved to x = 106 mm. USB notches at y = 32 and 68 mm.
  • Hand-placed: holders, gauge core (IC, shunt by BT101's − contact, protection FETs, fuse, and the VC filter ladder at the VC pins), the sleep-current section, MCU (antenna end at the top edge with a clear zone), connectors, and each charger power train. Port 2 is port 1 shifted 37 mm down.
  • Power train (per port): USB-side half-bridge Q401 with its input bank (4 × 22 µF MLCC + 68 µF polymer) straddling its drain and ground pads, inductor L401 between the two half-bridges, battery-side Q402 with its output bank (3 × 47 µF MLCC + 100 µF polymer), BQ25756 beside the inductor with its gate-drive pins facing the FETs and the bootstrap/REGN caps between them; input sense resistor toward the PD controller, output sense resistor and the 10 A link toward the pack bus.
  • The remaining ~200 small parts are auto-placed next to the pins they connect to (no courtyard overlaps). Worth a review pass in KiCad before routing.
  • Silkscreen: labels on test points (net name centred above every loop), connectors, jumpers and holders only; block titles (MCU, GAUGE, PORT 1, PORT 2, SLEEP CURRENT); "USB 1"/"USB 2" below the connectors.
• Placement (second pass, 2026-10-12): structured instead of nearest-free-spot. The ~200 small parts are no longer auto-placed; place_parts.py lists every one in PORT_LAYOUT / LAYOUT as rows and columns, and the auto placer is only a fallback (it places nothing now).
  • Support parts sit in rows on the side of the pin they serve, each row turned the same way (0/180 chosen so the signal pad faces its pin). BQ25756: FB divider, SRP/SRN filter caps and DRV_SUP left; ILIM/ICHG/TS/CE resistors above; ACUV/ACOV divider, FSW and the ACP/ACN filter caps right (C414 was 37 mm from the IC before). TPS25751: supply caps in a column on the left, the ADCIN straps (R1/R2 for port 1, R3/R4 for port 2, 0R to LDO_3V3 or GND; the DNP divider footprints R405–R408 were removed on 2026-10-14, as SafeMode at 0x20/0x21 needs only ties) with the EEPROM and its pull-ups above.
  • Port 2 is an exact copy of port 1, 37 mm lower (before, only the power train matched).
  • Hot loops first. Each half-bridge has its 0603 HF cap (C430, C438) straddling its drain and ground pads (0603 pad pitch = the FET's 1.6 mm drain-to-ground spacing); the 1210 MLCCs sit in one row right behind each FET (three on the input side, two on the output side), with one more MLCC stood on end beside each FET's drain edge, and the polymer bulk cap one row further back (since the polymer change below). The TPS62933 runs in one line, input bulk → 0.1 µF across VIN/GND (pins 3/4) → U404 → BST cap → L402, with the output caps above L402. The VBUS TVS D401 moved beside the CC caps at the connector to make room. L201 now touches the TPS62177.
  • Test points in labelled probe rows: each port has a 2 × 5 field under its power stage (SW1/SW2 straight below their inductor pads, STAT/PG pull-ups under their test points); VBUS and PP5V at the connector edge; pack and system signals in a 2 × 4 field in the gauge column; cell taps CELL_N–CELL3 in a column beside the holder contact each one measures.
  • Board NTCs where the spec puts them (they were all at the MCU): TH301/TH302 beside each port's Q402, TH303 between the USB-C connectors, TH304 in port 1's probe field.
  • Gauge: BAT/PBI/PACK/VCC parts in a row over the top pins, gate series and 10 MΩ resistors either side of each protection FET, SMBus resistors and BTP pull-up beside their pins.
  • Not changed: holders, gauge core, both power trains (apart from the cap banks), connectors, MCU module, sleep-section ICs. Known quirk of the hand placement: Q402's gate pins face away from U403 (the half-bridge package can't be mirrored), so HG2/LG2 need a route round or under Q402.
  • Run tools/setup_board.py after place_parts.py: KiCad's python save rewrites the project file with default rules.

Floorplan (board mm from the top-left corner):

• Holders: BT101–BT104 stacked at x ≈ 55, y = 15/43/71/99 (BT101 at the top, all the same way round).
• Gauge column (x ≈ 104–134): gauge, protection FETs, shunt, BQ294700 and F102, J101 and the EV2400 header.
• MCU band (top edge): SWD/UART/spare headers, then the CC2340R5MODA with its antenna end at the top edge (rev A7; was the STM32WB1MMC).
• Port bands: one 36 mm band per connector on the right (y ≈ 13–49 and 49–85).
• Sleep-current section (bottom edge): R_MEAS, INA190s, LDO and TPS62177, with test loops at the edge.

Status

• Rev A8 (2026-10-14): 429 parts. Review 4's hardware fixes (item 41) and its documentation, BOM and procedure items (item 42); every review 4 item is closed or decided. The board is updated to match (placement only): 0 parity issues, no courtyard overlaps.

• Rev A7 (2026-10-14): 411 parts. CC2340R5MODA MCU, TMP1075 sensors, one IRQ line (item 40). The board is updated to match (placement only).

• Rev A6 (2026-10-14): 416 parts. Changes since rev A4:

  • review 3 and liquid detection (item 36);
  • cost-down (item 37);
  • discrete charger FETs (item 38);
  • 6-layer board with the TPD4S201 (item 39).

• ERC: 0 errors, 8 warnings, all the same item: TPS25751 unused GPIOs tied to GND (TI's datasheet says to do this; KiCad flags a bidirectional pin on a net driven by the GND power flag). tools/check_overlaps.py reports 0 text overlaps.

• Board (routed 2026-10-17): routed and DRC-clean, fab outputs in fab/ (items 49–50); never ordered. The placement-stage notes from 2026-10-14 follow.

• Board (placement, 2026-10-14): every footprint placed by block, no courtyard overlaps, 0 schematic-parity issues. The other DRC items:

  • unrouted connections;
  • the footprints' default reference text on silkscreen (the silkscreen pass is still to do);
  • the U403/U503 library-mismatch warning (item 39).

  If KiCad has the board open, revert/reload it before saving.

• Cost (2 boards, 2026-10-15): bom_cost.csv (tools/bom_cost.py 2) gives $67.99 parts plus $40.50 JLC extended-part fees (27 unique extended parts × $3 ÷ 2 boards) = $108.49 per board. Before the fee cut (item 44) it was $124.28 (37 extended). At 5 boards the rev A8 BOM was $79.20. U301 (CC2340R5MODA) is costed at TI.com's $4.028 (qty 1-99; $2.189 at 1k+), consigned to JLC. JLC (C55046847) had 0 stock on 2026-10-14; TI.com has it in stock (2026-10-15, logged in; logged out it shows "Not available"). The STM32 module was $10.65. Not included: the PCB, assembly, shipping, cells, U201 and J301.

• PWR_FLAGs (the diamonds) sit where each rail is sourced through a passive part; each sheet's NOTES says so.

Changes from the circuit description (draft 5)

Found while checking against datasheets:

1. BQ40Z50-R2 VCC (pin 26) goes through 100 Ω to the CHG/DSG FET common-drain node (R106), as in TI's reference schematic (fig. 9-1, R13). The description said VCC needs no external parts.

2. BQ40Z50-R2 PACK (pin 27) has an external 10 kΩ to PACK_P (R113), as in TI's reference (R15).

3. TPS70950 output cap is 2.2 µF (C205), not 1 µF. The TPS709 datasheet asks for ≥ 2.2 µF.

4. BQ25756 VAC comes straight from PPHV (before the input sense resistor) with 1 µF. The old netlist's 10 Ω series resistor is gone; that matches TI's typical application.

5. BQ25756 DRV_SUP is fed from REGN through 10 Ω (TI typical application). The old netlist tied the two together directly.

6. BQ25756 sense filters follow the datasheet pin descriptions on both shunts: 10 Ω in each lead, 0.47 µF differential, 0.1 µF from each side to PGND.

7. STM32WB1MMC: PB0/PB1/PB2 unused. ST calls these three pins RF-sensitive and says not to connect them if possible (DS14096 §7). NTC_EN moved from PB0 to PA8, EN_5V1 from PB1 to PA11, EN_5V2 from PB2 to PA12 (design review 2026-10-11), so the 2.7 pF guard caps C305–C307 were removed and PB0–PB2 carry no-connect flags. ANT_IN/ANT_OUT are joined by a 0 Ω resistor (R303) for the internal antenna. NRST has 100 nF.

8. PP5V bulk: a 220 µF 16 V polymer cap (C443/C543, ChuangHui SS221M160E7R7R4Z00ZZ, C25503905) was added on each port's PP5V. The TPS25751 table lists 120 µF minimum on PP5V (USB PD cSrcBulkShared), after derating. 2 × 22 µF + 10 µF wasn't enough, and a 100 µF MLCC keeps only about a third of its value at 5 V; polymer caps don't lose capacitance with DC bias.

9. TPS62177 SLEEP → PB4 (net 3V3_SLEEP). After reset PB4 is the JTAG NJTRST pin with its internal pull-up on (DS13258 table 15 note 8), which beats the TPS62177's weak internal pull-down (1.4 µA at 3.3 V), so the 3.3 V rail boots in normal mode. That is the safe way round (sleep mode only supplies 15 mA). Firmware must make PB4 a push-pull GPIO before using sleep mode, and drive it low rather than leaving it floating. FB is tied to GND, which TI recommends for the fixed-output part.

10. Status LED on PB5: 1 kΩ, green 0603, and a 0 Ω (R307) to pull for sleep measurements. Spare header J303 carries PA7 (NTC_TH5 since rev A5), PB8 and, for probing or overriding, NTC_EN, EN_5V1 and EN_5V2.

11. Gauge VSS = CELL_N (TI: "IC ground should be connected to the 1N cell tab"). The system GND is on the other side of the 1 mΩ shunt.

12. TPS25751 capacitors checked against datasheet table 6.4 (values are after derating): LDO_3V3 (C404/C504) 4.7 µF 0603 → 10 µF 25 V 0805 (≥ 5 µF needed); LDO_1V5 (C405/C505) 4.7 µF → 10 µF (4.5–12 µF); VBUS (C406/C506) 1 µF 35 V 0603 → 4.7 µF 50 V 0805 (1–10 µF, a 1 µF 0603 drops below 1 µF at 20 V); VIN_3V3 (C403/C503) 10 µF is fine.

13. Fuse F101: prosemi 1206FA-8A (C21261118), 1206, 8 A fast, 32 V, 300 A interrupt at 24 V. That allows about 6 A continuous after 75 % derating, inside the description's 5–7 A. The 2410 7 A alternative only lists an AC interrupt rating. D101: BAT54WS (C7502694, JLC preferred part). Rev A4 (2026-10-12): changed to prosemi 1206FA-15A (C2838894), same footprint and interrupt rating (300 A at 24 Vdc; the pack never exceeds 16.8 V): the 8 A part only allowed about 6 A continuous, i.e. 60–70 W out, short of the 100 W goal (about 10 A from the pack at the 12 V low end). 3.9 mΩ, about 0.4 W at 10 A. Holder-mode current is now limited by firmware and the gauge settings, not the fuse.

14. INA190s (U201/U202) are hand-soldered, bought from DigiKey/Mouser (decided 2026-10-11). JLC had only 7 INA190A5 and no INA190A1, and the in-stock look-alikes (INA180/181/185/296) draw tens of µA of input bias, which flows through R_MEAS and swamps µA readings. Both parts are excluded from the position file and have no LCSC number, so JLC leaves the pads empty; MPN and a Sourcing note are in their properties. Update 2026-10-13: JLC now stocks INA190A1IDDFR (C1852068, 1,700), so U202 is JLC-assembled (LCSC set, back in the position file). U201 (INA190A5, gain 500; 7 at JLC) stays hand-soldered. INA190A4 (gain 200, C1852066) would be the JLC option for U201, at 2 mV/µA and about 2.5 mA full scale. The INA21x family is no substitute: 15–35 µA input bias through R_MEAS and no enable pin.

15. PPHV bulk above 100 µF is kept. The TPS25751 table limits sink bulk to 100 µF (USB PD cSnkBulkPd) unless VBUS surge current is limited. The TPS25751D's PPHV sink switch ramps with a slew-rate loop (§6.9: 0.35–0.47 V/ms at setting 0, up to 3.8 V/ms at setting 3), so the BQ25756 input bank (about 125 µF effective at 20 V since rev A5 made C421 100 µF, item 24) charges at about C × SS = 0.06 A (setting 0), 0.5 A worst case at setting 3. The TPS25751 configuration must use PPHV soft-start setting 0 or 1; this is in the usb_port sheet notes.

16. Charger bulk is polymer plus MLCC, not all MLCC (2026-10-12). The 1210 X5R banks lost most of their value to DC bias (a 22 µF 35 V keeps about 8.5 µF at 20 V, a 47 µF 25 V about 12 µF at 16.8 V), so meeting the BQ25756's ≥ 80 µF effective per side (datasheet §6.3, TI asks for "a combination of ceramic and bulk capacitors", §7.2.1.2.5–6) took 10 + 7 parts per port. Each bank now has one solid polymer cap for the bulk and keeps only the MLCCs that carry the switching-frequency ripple next to the FETs:

    • USB side (AC_SNS_N): C420/C423/C424/C427 22 µF 35 V 1210 + C421 polymer, 35 V. It was 68 µF here (ChuangHui SV680M350E5R8R4Z00ZZ, C49435121); rev A5 made it 100 µF (Honor HV1V107M0607PZ, C5246554, item 24), because the MLCCs keep only 5.9–6.8 µF each at 20 V (review 2, B-5). About 99 µF effective worst case. 35 V gives margin over ACOV (22.5 V) and the SMAJ22A clamp.
    • Battery side (BAT_SNS_P): C431/C434/C435 47 µF 25 V 1210 + C432 100 µF 25 V polymer, JIERR MA25V100M6x6 (C46550465), 6.3 × 6 mm, 30 mΩ, 2.65 A at 100 kHz. About 36 + 100 ≈ 136 µF effective at 16.8 V (≥ 116 µF at −20 %).
    • Removed per port: C422, C425, C426, C428, C429, C433, C436, C437 (16 MLCCs on the board).
    • Ripple: worst-case input RMS is ICHG/2 (§7.2.1.2.5); the MLCCs (a few mΩ each) take nearly all of it at 600 kHz, so the polymer's 2 A rating is not the limit.
    • Leakage (superseded by item 43: C432 is now a hybrid polymer, 25 µA max): C432 is biased from PACK_P whenever the gauge FETs are on. Solid polymer leakage is specified loosely (typically 0.1–0.2 CV, i.e. up to a few hundred µA, after 2 min); real parts are far lower, but measure the pack drain with and without C432 at bring-up. A hybrid polymer (for example Panasonic ZA/ZC, 0.01 CV) is the fallback if it matters.
    • This is the same structure as the production BOM (docs/monolith_port1_bom.csv, removed 2026-10-14; in git tag product-draft-2026-10-09: 4 MLCC + 68 µF polymer per side). The production polymer is a ≤ 5 mm D-case 25 V part on the 20 V input; 25 V at 20 V is tight for a polymer cap, so 35 V is used here.

17. Design-review fixes (rev A4, 2026-10-12) from ../../docs/devboard/schematic-review-2026-10-12.md. Item numbers refer to that review; its "Status" section lists every item.

    • #1 U203 EN is no longer tied to LDO_IN (PACK_P would have destroyed it); EN floats on its internal 300 nA pull-up.
    • #2 ICHG R413/R513 5.11k → 9.1k 1 % (revised from 17.8k, then 9.09k 0.1 %, the same day): 5.5 A hardware ceiling per port (5.3–5.8 A over K_ICHG and resistor tolerance), so a single port can charge at about 1C. The sum of both ports is kept at 5.6 A by configuration and firmware: the TPS25751 configuration starts each charger at ICHG_REG = 2.8 A, and the MCU raises the only charging port to the full rate and drops it back to 2.8 A on the other port's attach interrupt, before that port's PD contract closes PPHV. EN_CHG_BIT_RESET_BEHAVIOR = 0 and EN_ICHG_PIN = 1 in the configuration, so a watchdog expiry stops charging instead of falling back to the pin limit. Backstops: gauge OCC1 about 6 A, CHG_INH, F101. Set IPRECHG and ITERM by register (the pin only caps them at 20 % / 10 % of 5.5 A).
    • #5 U101 footprint is TI's RSM0032A land pattern (1.4 mm thermal pad, one 1.3 mm paste window), MonolithDev:TI_RSM0032A_...; KiCad's generic part had a 2.8 mm pad.
    • #6 D403/D503 ESD2CAN24 → PESD5V0S2BT (5 V, C49338, same SOT-23 pinout): D+/D− reach TPS25751 GPIO4/5, rated 6 V. CC keeps the 24 V part.
    • #7 R101–R104 → 1206; J101 is DNP; F101 was DNP (hand-fit after checking the cells) until rev A5, item 25. The cell-tap ladder is at 2.5 mm pitch.
    • #8 / m1 DNP footprints on Q102: C109 gate-to-GND (inrush), D102 across R111 (fast turn-off), D103 15 V gate–source clamp.
    • #9 SMBus pull-ups R304/R305 now hang off SMB_PU, fed from 3V3 by R312 (0R). Remove R312 and supply TP308 for EV2400 work while 3V3 is down.
    • #10 BTP_INT → Q103 2N7002 (R117 470k gate pull-down) → GAUGE_BTP: PA6 never sees the gauge pin's unbounded high level. GAUGE_BTP is now active low.
    • #11 U301 MPN STM32WB1MMCH6TR / C5456183 (LCSC had none in stock on 2026-10-12: check JLC or consign).
    • Minor: C105 2.2 µF 50 V 0805; C205 4.7 µF 25 V 0805; C409/C509 1 µF 50 V 0805; R433/R533 107k (PP5V 5.08 V) with a DNP 10 pF feed-forward cap C447/C547 across each; R431/R531 2512; R204/R205 49.9 Ω fitted; vertical SMAs (Amphenol 132134) for J201/J202; U204 NC pin to GND; IRQ1/IRQ2 100k pull-ups (R314/R315); 1k series resistors R316–R318 between the MCU and J303; reset button SW301; BOOT0 pad TP306; 3V3_SLEEP pad TP307 with a DNP 100k pull-up (R313); keyed SWD header (Samtec FTSH-105-01-L-DV-K, SMD footprint); "not GND" silk under TP102 and TX/RX/G over J302; MPN/LCSC/voltage ratings filled for the parts the review listed.
    • Wake + bench supply: SW101 (CELL_P → 4.7k → PACK_P) wakes the gauge from SHUTDOWN without USB; J104 feeds PACK_P from a bench supply.
    • Not changed: D401/D501 stay SMAJ22A (meets TPS25751 footnote 4; TVS2200 has no LCSC/JLC stock). R430/R530 stay copper net ties. FSW stays 600 kHz (production copy). No second-level protector on rev 1.

18. Open-question decisions (rev A4, 2026-10-12), see the review doc's "Decisions on the open questions":

    • CHG_INH: MCU PB8 → R435/R535 (1 k) → each BQ25756 CE. High stops charging whatever the TPS25751 does. (Rev A5 reversed the default, item 23: R417/R517 now pull CE up to 3V3, so the MCU must drive CHG_INH low to allow charging.) Firmware asserts it when the gauge is silent, misconfigured or implausible, or a protection FET is stuck on. J303 pin 6 reaches it through R319. This replaces the spare PB8.
    • J103 is 4-pin in the EV2400 SMBus order: 1 VSS, 2 SCL, 3 SDA, 4 not used.
    • "FIT CELLS BEFORE USB" on the silkscreen under the holders; with no cells the charger holds PACK_P at about 16.8 V.
    • Gauge configuration: 4S, FET_EN, precharge off (no external precharge FET), short OCD/OCC recovery delays.

19. Precision resistors rounded to stocked 1 % parts (2026-10-12). Only the two feedback dividers that set a voltage stay 0.1 %: R418/R419 (charge voltage, needs about ±1 %) and R433/R434 (PP5V, margin to the TPS25751's 4.9 V minimum). The rest move to UNI-ROYAL 1 % (all in stock at LCSC): R413 9.1k (ICHG 5.5 A), R414 3.6k (ILIM 5.6 A), R415/R416 1.8k/5.6k (TS network: hot 94.5 °C, warm 74 °C, cool 18.8 °C, cold −7 °C; an open NTC still reads as cold in charge mode, with more margin than before), R412/R410 40.2k, R409 137k (now 0603: no 0805 stock), R411 and R308–R311 10k. Unique 0.1 % parts drop from 10 to 4.

20. BQ25756 bootstrap diodes added (2026-10-12). TI's BQ25756 schematic checklist lists D2/D3, "BTST1/BTST2 diode-OR", as required Schottky diodes from DRV_SUP to each BTST node (the datasheet pin table only mentions the capacitor, and TI's typical application draws them). Each port now has D404/D405 (D504/D505): LRB521S-40T1G (LRC, C135802), 40 V 200 mA Schottky, SOD-523, anode on a new DRV_SUP label, cathode on the BTST cap. Placed in line with the BTST caps (D405 under C411 left of C413, D404 right of C412), clear of the SW1/SW2 copper. The production BOM (docs/monolith_port1_bom.csv, removed 2026-10-14; in git tag product-draft-2026-10-09) was missing them too and now lists D3/D4.

21. One NTC per cell (2026-10-12, rev 2 item 1 pulled into rev 1). Gauge TS2–TS4 are no longer tied to VSS: J105–J107 (2-pin, like J102) take a wired 10k 103AT NTC each, taped to BT102–BT104. All four headers sit beside the tap test point of the cell they watch (J102 moved from the gauge column to beside TP102). The welded pack's thermistors use the same headers. Keep the sensors insulated: each can is at its cell's negative terminal (up to about 12.6 V above VSS), the TS pins are rated 2.1 V. Enable TS2–TS4 in gauge data flash.

22. ESD caps across the protection FETs (2026-10-12). TI's BQ40Z50-R2 reference has two series pairs: C1/C2 (0.1 µF + 0.1 µF) across the back-to-back FET pair, cell side to pack side (sec. 9.2.2.1.1, fig. 9-2), and a second pair across PACK+/PACK− (sec. 9.2.2.1.5). Rev 1 only had the PACK pair (C107/C108, PACK_P to GND, unchanged). Added C110/C111 (0.1 µF 50 V 0603, C14663) from CELL_P to PACK_P, placed in the gap between Q101 and Q102; route them short and wide.

23. CHG_INH fails safe, plus a watchdog (rev A5, 2026-10-13; review 2 decisions D1–D3). R417/R517 changed from a 10k pull-down to a 47k pull-up to 3V3 (C25819). The MCU drives CHG_INH (PB8) low to allow charging; high, hi-Z, reset, a hang or an unprogrammed MCU all stop charging at CE. A dead pack still recovers from USB: with 3V3 down, CE reads low. Levels: MCU low gives CE = 3.3 V × 1k/48k = 0.07 V (VIL max 0.4 V); hi-Z gives about 3.25 V (VIH min 1.3 V). A 10k pull-up would only reach 0.30 V low. Charging needs the MCU in Run or Stop0–2 (GPIO state held), never Standby. PB8 low costs 138 µA (two 47k pull-ups), so it is low only while charging and high in idle. The full pin-by-state plan, reconciled with the 150 µA sleep budget, is ../../docs/devboard/mcu-io-power-states.md. A hang is cleared by the STM32 IWDG in hardware mode (option byte IWDG_SW = 0): it starts at every reset, firmware cannot stop it, and it runs from the LSI clock. During the reset CE goes high, so charging pauses until firmware allows it again. Bring-up consequence: flash the MCU before testing USB charging. Other decisions: ICHG stays 9.1k (5.5 A, D2); F101 stays 15 A on the condition that the gauge cut-off under load is 2.8 V/cell or higher (D3).

24. Review 2 follow-ups (rev A5, 2026-10-13).

    • BAT fed from the cell top, as TI fig. 9-12 (D1 on 4P): D101 anode moved from CELL_P (after F101) to CELL_P_RAW, the VC4 Kelvin node. The gauge stays powered and logging if F101 opens or before it is fitted. Consequence: a meter across the F101 pads no longer sees the gauge's own supply current.
    • USB-side bulk C421/C521: 68 µF → 100 µF 35 V polymer (Honor Elec HV1V107M0607PZ, C5246554). Same 6.3 mm footprint, 7.7 mm tall. About 99 µF worst case against the BQ25756's 80 µF minimum after derating (was 72–75 µF). Datasheet: ESR 48 mΩ, ripple 1.5 A rms. Worst-case bank ripple is about 5 A rms (reverse mode, 10 V pack boosted to 20 V at 5 A); the four 22 µF MLCCs (about 11 mΩ at 600 kHz) take about 80 %, so the polymer sees about 1 A rms (about 50 mW).
    • Bootstrap diodes → LRB520S-40T1G (C132124, same SOD-523): 9–20× lower reverse leakage.
    • Q103 → BSS138 (onsemi, C52895): Vgs(th) max 1.5 V against about 2.6 V guaranteed BTP_INT drive.
    • C109 (DNP) → 4.7 nF: 0.1 µF would slow Q102's short-circuit turn-off past its SOA. Its note says to fit D103 whenever C109 is fitted.
    • New HF caps: C449/C549 0.1 µF on each TPS25751 PPHV; C450/C550 10 nF on VBUS by the receptacle (TI layout example).
    • New test points:
      • GND scope-ground loops: TP412/TP512 beside each port's SW1/SW2 probes (TH304 moved 1 mm left), and TP109/TP309 in a third row of the pack probe field.
      • TP108 on CELL_P_RAW, beside F101.
      • Small pads: TP413/TP513 CE_N (beside R435), TP414/TP514 LDO_3V3, TP206 LDO_IN, TP207 5V_AMP.
    • R306 1k → 330 Ω: about 1 mA in the InGaN status LED instead of 0.5 mA.
    • C201 is now flagged DNP (its value already said so).
    • JLC numbers on every resistor and capacitor: UNI-ROYAL and Samsung/FH basic parts where they exist. Values whose rating changed to match the stocked part:
      • 0.1 µF 25 V → 50 V;
      • C407 10 µF 10 V → 25 V;
      • C207 22 µF 10 V → 25 V;
      • C410/C411 4.7 µF 16 V → 25 V;
      • C441/C442 22 µF on PP5V, 35 V → 25 V (5 V net).

25. F101 is JLC-placed again (rev A5, 2026-10-13). Hand-fitting it meant soldering next to an installed 16.8 V stack with no fuse, and since item 24 (BAT fed before F101) leaving it off no longer disconnected the gauge either. The loads were never at risk from it: everything is on PACK_P behind Q101/Q102, which stay off on a fresh gauge (FET_EN off, Mfg Status Init 0x0000). A reversed or missing cell finds no path (the DSG FET body diode blocks discharge, the CHG FET body diode blocks charge). Procedure:

    1. Insert the cells.
    2. Check each cell at TP102–TP105 and the stack at TP108.
    3. Only then wake the gauge (SW101, J104 or USB) and configure it (precharge thresholds, then FET_EN).

    Given up: measuring total pack drain across the F101 pads. Use R_MEAS for the 3V3 branch and the gauge's current reading for the rest.

26. SMD test loops instead of Keystone through-hole (rev A5, 2026-10-13). All 45 loop test points are now ronghe RH-S2761-46R (LCSC C55121754, about $0.12–0.20 each, about 10k in stock): an SMT loop 1.60 × 0.80 × 1.15 mm on an 0603 land pattern, the JLC-stocked equivalent of the Harwin S2761-46R (3.5 A). Footprint MonolithDev:TestPoint_Harwin_S2761_0603 (tools/make_footprints.py section 11): two 0603 pads, both pin 1 and marked jumpered, since the loop joins them. JLC places them with the rest; no through-hole assembly. They are small: fine for hook probes and mini-grabbers, but too small for a scope's alligator ground clip, so use a ground spring or a short ground lead on the GND loops. The bare 1.5 mm probe pads (TP306, TP307, TP413/TP513, TP414/TP514, TP206, TP207) stay pads.

27. Open-item pass (rev A5, 2026-10-13).

    • D104 SS34 (C8678) in series with the J104 bench input: blocks a reversed lead, and keeps a live PACK_P off the bare header pins.
    • D401 is drawn with a zener-style (unidirectional) symbol, cathode on VBUS.
    • Headers have JLC numbers (XFCN PZ254V-11 family, like J102): J103 4P C2691448; J302 and J402/J502 3P C2937625; J303 7P C492406; JP201 2P C492401.
    • Shunts: JP201/JP202 notes say each needs a 2.54 mm shunt (hand).
    • J301 notes now say keyed shroud, all pins fitted (not "pin 7 removed").
    • Sheet text: port sheet "5.08 V" and "ILIM 5.6 A".
    • Thermistor notes: state Murata B25/50 = 3380 K / B25/85 = 3435 K; use the R-T table.
    • Gauge note 4: insulated cell NTCs only.
    • Antenna keep-out rule area on the board.
    • Power budget by state: ../../docs/devboard/power-budget.md.
    • Bring-up checklist: ../../docs/devboard/bringup-config-checklist.md gathers every configuration item, with review 2's precharge correction.

28. TH305 at the protection FETs (rev A5, 2026-10-13; review 2 A-7). Q101/Q102 dissipate about 1 W each at 100 W and nothing sensed them. TH305 (same Murata 10k NTC) sits between the two FETs right of C111, on PA7 (ADC1_IN2) with the same 10k 1 % / 0.1 µF divider from NTC_EN as TH301–TH304 (R320, C312 under J303). The PA7 net is now NTC_TH5 and still reaches J303 pin 2 for probing. Firmware: include it in the over-temperature and gauge cross-checks. It can be left unpopulated later.

29. Footprint checks and 3D models (2026-10-13).

    • Cell holder footprint fixed. Rendering the MYOUNG drawing showed a dia 2.25 hole for the + terminal's locating tab: the side view has a fork below the seating plane, 38.60 mm from centre. The footprint lacked it, so the holder would have sat on its tab. Added as NPTH at (-38.6, -11.5) and refreshed BT101-BT104; the silk gaps around it. Pads (7.5 × 9.0, 93.6 outer) and pegs (dia 4.0 at ±34, 8.5) were already right.

    • J301 uses Samtec's recommended land pattern for FTSH-1xx-xx-xxx-DV (rev G): 0.74 × 2.79 pads at ±2.035, courtyard covering the -K keying shroud. New footprint MonolithDev:Samtec_FTSH-105-01-xx-DV-K_2x05_P1.27mm. J301 moved 1.2 mm left; the "MCU" title moved below it.

    • 3D models on 346 of 362 footprints (every physical part). Custom footprints borrow same-body KiCad models (make_footprints.py MODELS, pin 1 checked in a 3D render; KiCad turns positive Z angles clockwise):

      • QFN-32 4×4 (U101);
      • QFN-36 5×6 (BQ25756);
      • WQFN-40 6×4 (TPS25751; KiCad has no REF0038A model);
      • VSON-8 3.3×3.3 at 270° (AGM404AP1);
      • TDSON-8-1 at 270° (half-bridge; single-FET body);
      • the 1.27 mm 2×5 SMD header (J301).

      place_parts.py re-points a KiCad-library footprint whose model KiCad 10 does not ship: the TS-1187A switches use the TL3342 model (same 5 mm 4-pad tact).

      USB-C (J401/J501) model, measured from the maker's vector drawing. No STEP file exists from ShouHan, LCSC/EasyEDA (listed with no device) or the usual aggregators.

      • How it was built: tools/drawing_extract/ pulls the outline strokes of every view out of ../../datasheets/usb-c-16pcb0.8-ip68.pdf, scaled at 10.888 pt/mm (cross-checked against the 10.25, 9.64, 7.45, 8.34 and 2.56 dimensions). tools/make_3d_usbc.py builds the solids from those measurements (OpenCascade).
      • Verification: tools/verify_3d_usbc.py projects the model with hidden-line removal and overlays it on the drawing. Front, top and side views coincide; see 3dmodels/verification/usbc_overlay_*.png.
      • Key numbers:
        • receptacle centreline 0.827 above the board top;
        • body bottom flush with the 0.8 mm board bottom;
        • seal ring 10.25 × 4.45 with R0.2 edges, 0.50–1.50 behind the mating face;
        • mating face 1.949 outside the board edge;
        • legs: 0.2 sheet, shelf on the board top, foot to the board bottom at x ±5.80.
      • Drawing inconsistencies, all within its tolerances: the front view draws the ring 10.36 × 4.35 against the dimensioned 10.25 × 4.45 (dimension used). Leg tips are drawn 11.81 apart against 11.60 ±0.25 (drawn geometry used; it matches the footprint slots).
      • Assumed (not defined by the drawing, all inside the envelope): cavity depth, tongue, body corner R0.3. Shallow surface details (latch window, leg channels in the shell sides) are left out.
      • For the enclosure: the envelope is accurate to the drawing. The drawing's own tolerances are ±0.15–0.25 mm, so confirm critical fits (seal compression, wall opening) with calipers on a sample, or ask ShouHan for their STEP.

      Cell holders (BT101-BT104) and cells: tools/make_3d_holder.py.

      • Source: LCSC's EasyEDA model (3dmodels/source/, a SolidWorks export; MYOUNG publishes none), checked against MYOUNG's drawing by hidden-line overlay. Its top view matched.
      • Corrected:
        • side walls clipped to the drawn profile (ends 15.62, shoulders 9.84, centre dip 6.88; EasyEDA's middle walls were 1.0-1.5 mm too high);
        • end-slope wall strips filled out to the drawing (EasyEDA's were 1.0-2.3 mm short);
        • EasyEDA logo removed;
        • • terminal locating tab added: 1.50 wide, 1.20 below the seating plane, 11.5 off the axis. The drawing's "11.5 ±0.35" is this tab, not the cell height.
      • Result: both views now coincide with the drawing.
      • Cell: a separate STEP for the EVE INR21700/58E (Ø21.50 × 70.80, + end per EVE fig. 1), attached as a second model on the holder footprint.
      • Cell axis height is PROVISIONAL: Z = 13.18 (EasyEDA cradle floor 2.6 plus the cell radius). MYOUNG's drawing does not give it. Measure a populated holder (cell top above the board) and set CELL_AXIS_Z.

      STM32WB1MMC, M24512 UFDFPN8 and the SMT test loops: tools/make_3d_simple.py, envelopes from the package drawings:

      • STM32WB1MMC: 10.0 × 6.5 × 1.372 mm. Uses LCSC's EasyEDA model (3dmodels/source/), checked against ST's fig. 11 and table 3: envelope, 1.372 height, centre-pad cluster and inner pad row match the footprint. ST's own CAD models are behind sign-in (UltraLibrarian, SamacSys, DigiKey/SnapMagic); drop that STEP into 3dmodels/source/ to replace it;
      • M24512: 3.0 × 2.0 × 0.55 mm;
      • test loop: 1.6 × 0.8 × 1.15 mm.

      Coverage: 346 of 362 footprints have models. The rest are mounting holes, bare probe pads and the copper net-tie links, which are not physical parts.

30. Silkscreen purpose and pinout labels (2026-10-13). tools/place_parts.py PART_LABELS / PIN_LABELS (0.8 mm text; placed before the test-point and reference labels so they get the spots next to the pins):

    • Part labels: SW101 WAKE, SW301 RESET, JP201 AMP EN, JP202 MEAS PWR, J301 SWD.
    • Pin labels: J101 B- C1 C2 C3 B+; J102/J105/J106/J107 TSn and - (CELL_N); J103 GND SCL SDA NC; J104 + -; J303 3V3 TH5 NTC 5V1 5V2 INH G; J402/J502 SDA SCL G; J301 pin 1.
    • Placement rules: pins in a column get text turned along the column, and a row's labels stay on one side (nudged up to 1.5 mm off the footprint's own marks). Connector references boxed in by their pin labels drop to 0.8 mm or sit in line with the label column (J402/J502).
    • J302 (TX RX G) was already labelled.

31. Sleep-current outputs on test loops instead of SMAs (rev A5, 2026-10-13). J201/J202 (vertical SMAs) are removed. OUT_LO and OUT_HI are probed on their existing loops TP201/TP202. Each has its own GND loop 4.5 mm away (TP208/TP209, same RH-S2761-46R, JLC-placed) for a short probe ground lead. The four sit in a row on the bottom edge under the amps: OUT_LO, GND, OUT_HI, GND. R204/R205 49.9 Ω stay: they keep probe and cable capacitance off the INA190 outputs (1 nF max). Use a 1 MΩ scope input. Nothing is left to hand-fit in this section except U201/U202.

32. Routing started: net classes, planes, port power stages (2026-10-13).

    • Kelvin net class (0.2 mm track, 0.15 mm clearance: the gauge QFN's pins are 0.18 mm apart): each charger's filtered ACP/ACN/SRP/SRN, the gauge's SRP/SRN, VC1-VC4, BAT and PACK. The raw tap ends of the sense lines share the power nets, so a class can't enforce them: they are routed from the sense-resistor pads by hand.
    • Placement fixes for routing: RBAT (R427/R527) turned 180° so its VBAT_SYS pad faces the R430 link (the 9.5 A path no longer U-turns around the resistor) and its BAT_SNS_P pad faces the output caps. The SRP/SRN series resistors (R428/R429, R528/R529) moved out of the output-current path to beside RBAT, each next to the pad it senses.
    • tools/route_power.py (re-runnable; it rebuilds only what it added, listed in tools/route_power.uuids). For each port:
      • SW1/SW2 are compact F.Cu pours from the FET switch pads to the inductor, and the SW test loops are short stubs off the far side of the inductor pads.
      • Each input and output bank is an F.Cu pour mirrored on B.Cu and stitched with vias.
      • GND islands under the FET sources and cap grounds are stitched straight into In1, 0.1 mm below.
      • Cap pads that a bank pour surrounds get small pockets with their own vias.
      • VBAT_SYS runs straight from RBAT to R430.
    • Planes: In1 is solid GND and In2 is GND fill for now, both inset 0.5 mm from the edge.
    • Mounting holes: H1-H6 get a 6.4 mm copper keep-out on every layer, clear of the M3 screw head and washer.
    • TPS25751 footprint: the exposed pads' thermal vias now join the planes solidly. Thermal reliefs blocked the heat path and pinched the GND plane between the GND and PD_DRAIN via rows.
    • DRC: 0 violations.
    • Gate drive (BQ25756). All eleven drive pins sit on one 0.5 mm-pitch edge, in a different order from the FET pins (Q402's gates face away from the IC), so:
      • Every gate drops through a via right under its pin. HG1 runs on In2 with its SW1 return stacked under it on B.Cu, and LG1 on In2 under the In1 GND plane. HG2 and SW2 run side by side on B.Cu (outer/inner, so they never cross), and LG2 on In2.
      • Gate lanes are 0.5 mm wide (TI's 20 mil minimum).
      • The bootstrap loops stay on F.Cu with no vias: C412/C413 sit right under their BTST/SW pins with the BTST pad inner.
      • DRV_SUP and REGN run on F.Cu under C413 to C411, R420 and C410, now stacked left of the IC between Q402 and L401.
      • The bootstrap diodes D404/D405 moved right of C412 and are fed through In2 (DRV_SUP) and B.Cu (BTST).
      • The exposed pad gets 12 thermal vias, and PGND ties to it.
      • Placement uses a new ("fix", ...) entry in place_parts.py: exact rotation, no automatic 0/180 flip.
    • USB-C power path.
      • VBUS runs from J401's VBUS pads through via clusters into a B.Cu pour, then back up beside U401 into an F.Cu band over C406's VBUS pad to the VBUS power pad.
      • PPHV runs from U401's PPHV pad down a 1.75 mm F.Cu corridor (mirrored on B.Cu, 12 vias) to RAC. It feeds the pad from the right so R425's Kelvin tap lands on the pad's quiet end. R426's tap reaches the AC_SNS_N pad's outer end through In2.
      • J501 sits 36 mm below J401 (the rest of port 2 is 37 mm down), so the connector-side copper has its own offset.
    • C407/C507 (TPS25751 PP5V cap) is now 0603: Samsung CL10A106MA8NRNC, LCSC C96446, same 10 µF 25 V. It moved above U401 beside the PP5V pin. The 0805 sat in front of U401's VBUS power pad, so 5 A VBUS had no way in.
    • 5 V bucks (TPS62933):
      • C446 straddles VIN/GND (pins 3/4), with the 10 µF pair beside it.
      • SW runs straight to C440 and L402.
      • SS and BST share the gap between the pin column and C440: SS turns up first and BST passes under its corner.
      • FB is taken from the output caps (divider top at the regulation point); EN and SS fit in the remaining gaps.
      • 5V_IN runs from the R431 link along y 48.
      • PP5V (3 A when the port sources 5 V): L402 → C441/C442 on F.Cu, then up the right edge on In2 + B.Cu between J401's pads and its shell, to C443, TP403 and U401's PP5V pin through C407.
    • Pack path (11 A), in route_power.py's pack section:
      • Cell links: CELL1–CELL3 are 8.5 mm diagonal bands on F.Cu and B.Cu under the holders, from one holder's + pad (left end) to the next holder's − pad (right end), about 1 mΩ each. The holders all face the same way, hence the diagonals.
      • CELL_N: a 7 mm block from BT101's − pad into RS101, which is now turned so its CELL_N pad faces the cells and its GND pad drops into a 12-via field in the GND planes. A column between the NTC headers and R101–R104 carries CELL_N down to the welded-pack connector J101 pin 1. That column is about 5 mΩ (0.6 W at 11 A, welded-pack mode only).
      • CELL_P_RAW: a strip under BT104's body (below its pads) on F.Cu and B.Cu. It passes under the CELL_N column to F101 and runs along J101's pins to pin 5.
      • CELL_P: from F101 up between the pack probe columns on F.Cu, under the gauge on B.Cu, then into Q101's source pins from the left.
      • FET_MID: Q101 and Q102 face the same way, so their drain pads join on B.Cu through a 3×3 via grid in each pad (18 vias, also their heat path).
      • PACK_P: from Q102's source pins through an F.Cu strip to a B.Cu bus beside the port-1 output bank. The bus feeds R430/R530 (6 vias each), R431/R531 (5 V buck inputs) and the bench-supply diode D104.
      • One zone outline per net per layer: overlapping same-net zones with different priorities don't merge.
    • GND fanout (tools/fanout_gnd.py, branch dev-board-autoroute):
      • Puts one via beside every SMD GND pad not already on GND copper (144 vias), each spot clear of every other net on all layers, the edge rule and the antenna keep-out.
      • Re-runnable, using tools/fanout_gnd.uuids.
      • Kelvin ends (R108/R208) are skipped. U401/U501 GND pins 31/36/37 tie into the exposed pad instead.
      • The RBAT and RS101 Kelvin taps are hand-routed. The RS101 pair runs on In2 to R107/R108.
    • Routing workflow:
      • Order (KiCad 10's python, each script re-runnable and owning the items listed in its .uuids file):
        1. place_parts.py
        2. route_power.py (power, gate drive, Kelvin taps; hand-planned coordinates)
        3. fanout_gnd.py
        4. kicad-cli pcb drc (to a report)
        5. route_signals.py <report> (A* signal router)
      • Re-running an earlier step means re-running the later ones.
      • route_signals.py must get the DRC report of the board before its own tracks, since it removes them first.
      • Kept out of the router: the nets in its HAND list (sense pairs, MEAS±, antenna feed), which are routed by hand.
      • Re-runs strip as text: route_signals.py and fanout_gnd.py remove their old tracks by editing the board file as text before loading (tools/pcb_text.py). Mass removal through pcbnew leaves dead SWIG wrappers, and once (right after a place_parts.py run) it silently left all 288 old fanout items in the saved board.
    • Sense pairs and small hand routes (route_power.py, branch claude-router): all DRC-clean before the signal router runs.
      • SRP_F/SRN_F (charge current):
        • From RBAT's taps R428/R429 straight down to In2, under the In1 plane.
        • Runs as a 0.5 mm-pitch pair along y 16.6/17.1, above the output bank's via field, to C417–C419 and U403 pins 13/14.
        • The filter caps' pads alternate (SRP|SRN, GND|SRN, GND|SRP), so SRP surfaces twice (at C417 and below C418) and SRN once.
        • SRN stays the outer lane at both ends, so the pair never crosses.
      • FB/FBG: the divider R418/R419 has FB above FBG, but the pins have FBG on top. FB drops to In2 down the gap between the caps and R414.
      • ACP_F/ACN_F (input current):
        • From R425/R426 beside the PPHV corridor, both legs on In2.
        • Up the strip between the AC bank's via field and U401, then west above the HG1 lane to C414–C416 and pins 29/30.
        • ACN is the inner lane at both ends.
        • On F.Cu, ACN passes under C415's GND pad.
      • Gauge SRP/SRN: from R107/R108 to C106 and U101 pins 6/8 on F.Cu. SRN goes up the 0.69 mm gap between C104 and C106.
      • MEAS_P/MEAS_N:
        • Kelvin taps run straight up from shunt R201 to R202/R203.
        • The pair runs east, down the right of C201/R204, back west between R204 and R205, and down beside U202. MEAS_N is the inner lane at both amplifiers.
        • MEAS_P's link to C201/U201 has to cross MEAS_N, so it hops on In2 (two vias).
      • RF:
        • R303 is turned 180° (place_parts fix) so the module's antenna pin (6) and RF output (7) reach its pads without crossing.
        • Pin 6's track stays just below the antenna keep-out.
      • MCU fanout (STM32WB1MMC):
        • The BOOT0/NRST/decoupling column and the LED/3V3 column moved 1.2–1.7 mm left, and the I2C/IRQ pull-up column and R312 0.8 mm right. That opens a 2 mm via channel on each side of the module.
        • Every side signal pin gets its own via in two staggered columns (1 mm pitch each, 0.15 mm tracks, 0.175 mm clearance). The router continues from the vias.
        • IRQ1 runs straight to its pull-up. The 3V3_MCU pins link to C301–C303 under the left via field.
      • USB-C front end (both ports), reworked:
        • Placement: the VBUS TVS D401 sat directly in front of the connector's CC/DP/DN pins, and U401's VBUS-sense track ran over its CC/DP/DN pins. Both blocked those lines completely. The front-end parts (D401–D403, C401, C402) are now placed from the connector (CONN_EXTRA), so port 2's copy follows J501's 36 mm offset:
          • D401 lies below the signal rows, its VBUS pad on the lower VBUS pins (VBUS_J).
          • D403 sits in line with the data pins.
          • C450 now spans the VBUS strip.
        • DP/DN: the connector's interleaved DP/DN pins join with one In2 hop (A6 → B6's line). That frees a row, so the DN pins merge on F.Cu and the pair passes straight through D403's pads.
        • CC lines: CC2 rises into D402/C402. CC1 runs under D403 to D402. C401 (boxed in by CC2) joins CC1 on In2.
        • U401 corner: pin 32's VBUS link now goes through a via and B.Cu. The PP5V run on In2/B moved up (y 16.9–18.9, with a tab to pin 34). The four pins escape to a via row and four In2 lanes run east and down to the front end without crossing.
    • Autorouter tried and rejected (2026-10-13):
      • tools/autoroute.py runs Freerouting 2.5.0 (Java 25; the native CLI build crashes) with the power routing locked.
      • Five passes plateaued at 211–264 of 637 connections unrouted.
      • The single-pass result broke DRC in 42 places (0.05 mm via rings, 0.12 mm tracks), altered locked items, and ran the sense pairs and signals across the power stages.
      • Reverted. The signals will be hand-routed instead. The script is kept for reference.
    • State when paused (2026-10-13, branch claude-router): the board holds placement, power, hand-routed sense pairs / MCU fanout / USB-C front end and the GND fanout, but no router tracks.
      • DRC: 0 errors except 13 dangling MCU fanout vias, which wait for the router.
      • The last full router run (before the USB-C rework) reached 250 of 379 connections.
      • Paused for a schematic-first manual review. Re-run the workflow above after schematic changes.
    • Still to route:
      • the small PPHV taps (VAC pins, ACUV divider, C409, TP402) and REGN to R415/TP404;
      • then the signals.

33. Second-level protection: BQ294700 + chemical fuse (2026-10-13, branch hand-review). Reverses the 2026-10-12 decision to rely on software as the second layer (rev2-changes.md 1b). Hardware now guards per-cell overvoltage independently of the gauge, its data flash and the MCU, as in TI's BQ40Z50-R2 reference (datasheet fig. 9-11, BQ2947 fig. 8-1). Gauge sheet, new block "SECOND-LEVEL PROTECTION":

    • F102, TLC Electronic WSFB1514 (C42463217, about 3,900 in stock), a 3-terminal self-control fuse, sits in the cell-top path: CELL_P_RAW → F102 (pin 1 → pin 2) → CELL_P. Pin 3 is the heater.
      • Ratings: 4-cell part (UL E467707), 15 A at 40 °C, cuts in under 1 min at 2× rated current, 50 A interrupt, 36 V.
      • Heater: working range 10.5–19.6 V. TLC gives no heater resistance; the Littelfuse part with the same range is 11.2–20 Ω, and Q104 has ample margin.
      • Losses: its 1–3 mΩ fuse path adds about 0.2 W at 10 A.
      • Why this part: it replaced the Littelfuse ITV4030L1415NR first chosen: same 4 × 3 mm land pattern, a fifth of the resistance, and plenty of stock (LCSC had only 15 Littelfuse parts). The Littelfuse part, or Eaton SCF4030-15-04, could still fit the same pads, but both number their pins differently (fuse 1–3, heater 2), so the symbol and footprint would change. Not the WSFB1524 (C42463216): that is the 6-cell version, whose heater needs 17.3–28 V.
      • F101 deleted (2026-10-13, after F102 went in): F102's 15 A element is now the pack's only fuse, as in TI's reference (no separate fuse).
        • Trade-off accepted: F102 interrupts 50 A, while a dead short across the cell top before Q101/Q102 can reach about 200 A (4 × ~20 mΩ cells). F101 (1206FA-15A) could break 300 A. Shorts after the FETs are cleared first by the gauge's short-circuit protection (Q101/Q102 open within microseconds).
        • With R127 fitted (bench only) the pack has no fuse at all.
        • Items 13 and 25 above describe the old F101.
    • U102, BQ294700DSGR (C414622, JLC extended): 4.35 V/cell overvoltage trip, 0.30 V hysteresis, active-high output (about 7 V).
      • Its own 1 kΩ + 0.1 µF filter ladder on the cell taps (R119–R122, C112–C115). TI calibrates the device with 1 kΩ.
      • VDD from the cell top through 100 Ω + 0.1 µF (R123, C116).
      • CD 0.1 µF (C117) gives a 1–2 s delay. An open or shorted CD also trips the output during an overvoltage.
      • The trip point sits above the gauge's own cell overvoltage setting (about 4.3 V) and the 4.2 V charge voltage.
    • Ignition: U102 OUT → R124 5.1 kΩ → Q104 gate ← R126 5.1 kΩ ← gauge FUSE pin (net GAUGE_FUSE). R125 51 kΩ ∥ C118 0.1 µF pull the gate to CELL_N.
      • Q104 is an AO3400A (C20917, JLC basic): 30 V, Vgs max ±12 V; its gate sees at most about 8 V.
      • Q104 sinks the heater current (0.5–1.5 A) from F102 pin 2 to CELL_N, which blows both fuse elements.
      • The gauge FUSE pin was tied to VSS. It now both blows the fuse on a permanent failure and sees U102's trip (it reads the pin as an input).
    • R127, 0 Ω 2512, DNP: a bench-only bypass across F102 for a blown part (a ≥ 10 A 0 Ω jumper or an AWG18 wire). Never fitted on a pack in use, because it defeats the second level.
    • A trip is permanent: F102 opens and must be replaced. The gauge stays powered from the cell top through D101 (BAT feed from CELL_P_RAW), so its logs and permanent-failure flags remain readable.
    • Parts: passives are JLC basic parts (1k C21190, 100 Ω C22775, 5.1k C23186, 51k C23196, 0.1 µF 50 V C14663).
    • Library: new symbols BQ294700 and WSFB1514 (tools/make_symbols.py), footprint TLC_WSFB_4x3mm from the datasheet land pattern (tools/make_footprints.py section 13), and a 3D box model (tools/make_3d_simple.py).
    • Firmware / data flash, to do:
      • Enable the gauge's fuse-blow and permanent-failure settings (FUSE pin use, Fuse Failure, and the secondary-protector input). The secondary-protector input is checked against TI's technical reference manual.
      • Decide which permanent failures blow the fuse.
      • Make the MCU read the gauge's permanent-failure status so a blown F102 is reported, not just a dead pack.
    • Layout: not on the board yet.
      • Placement and routing must put F102 where F101 was, at the end of BT104's CELL_P_RAW strip, with Q104 beside its heater pad and U102 near the gauge.
      • place_parts.py and the pack-path copper (route_power: CELL_P_RAW strip, F101 pads, CELL_P) still reference F101 and have to change, then re-run the routing workflow above.

34. D103 fitted (2026-10-13, dev board and production). The 15 V Zener from Q102's gate (DSG_G) to its source (PACK_P) was DNP since review 1 (m1), as an option tied to C109. It is now placed (BZT52C15, SOD-123, LCSC C173427).

    • Why: in a hard PACK_P short, Q102's source falls to about 0 V while DSG holds the gate at VBAT + 10.5–12 V until the short-circuit trip opens the FETs (SCD1 delay up to 915 µs). That approaches about 28 V gate-source against the AGM404AP1's ±20 V.
      • Without C109, the gate partly follows the source down through the FET's own capacitance and the weak DSG pump recharges it slowly, which is why it was optional.
      • With C109 (still DNP) the gate is held up and the clamp is mandatory.
      • Fitting it always also covers fast PACK_P transients (connector shorts, ESD).
    • No effect in normal operation: the Zener's 14.25 V minimum (BZT52C15 datasheet, at 5 mA) sits above the 10.5–12 V on-state gate drive, and its leakage at 12 V (tens of nA) is well within the pump's drive.
    • TI's reference (BQ40Z50-R2 fig. 9-2) has no gate clamp. This is an addition, not a departure from a required part. Keep the SCD1 delay short in data flash as well.

35. USB-C liquid detection (2026-10-14, both ports), TPS25751 datasheet sec. 9.2.2.2 / fig. 9-8. The product is sealed (IP65 enclosure, IP68 connector), but the receptacle cavity still gets wet. Water bridging VBUS to CC/SBU corrodes the contacts, and water between CC and GND can look like an attached sink and make the port turn VBUS on.

    • How it works: the TPS25751 measures the SBU1/SBU2 pins (unused until now) through its GPIO4/GPIO5 ADC inputs. GPIO6 and GPIO7 switch a 100 kΩ pull-up (AO3401A Q403/Q404 + R436/R437, from LDO_3V3) and a 1 MΩ pull-down (AO3400A Q405/Q406 + R438/R439) on each sense line.
      • If the voltage says SBU is wet or shorted, it disables the power paths and reports a liquid-detected event over I2C.
      • It keeps sampling and recovers by itself when the receptacle dries.
    • U405 (now TPD4S201, item 39; first a TPD2S300YFFR, C2650411, DSBGA-9 0.4 mm): its short-to-VBUS OVP channels sit between SBU1/SBU2 and the sense nodes. They protect GPIO4/5 (6 V max) and LDO_3V3 if liquid bridges VBUS (up to 20 V) to SBU.
      • VPWR is on LDO_3V3 with 1 µF (C452). (The TPD2S300's VM pin and C453 went with the swap.)
      • VBIAS has 0.1 µF 50 V (C451). FLT goes to GPIO3 since review 3 (item 36).
      • Symbol TPD2S300 and footprint TI_YFF0009_DSBGA-9_P0.4mm stay in the libraries, unused since item 39.
      • Place it close to the connector.
    • BC1.2 is given up: GPIO4/5 are the TPS25751's D+/D− pins, so it no longer does BC1.2. D403 (D+/D− ESD) is removed.
      • R440 (0 Ω) shorts D+ to D− at the connector instead: a passive BC1.2 dedicated-charging-port signature, so legacy devices behind adapter cables still draw full current when the bank is sourcing. DNP R440 to leave D+/D− open.
      • Sinking from an old USB-A charger without BC1.2 is limited by the cable's Rp (default USB power), which is acceptable.
    • TPS25751 configuration (Application Customization Tool):
      • GPIO6 event = liquid_pmos_control (155) on net LIQ_PU; GPIO7 event = liquid_nmos_control (156) on net LIQ_PD. TI's EVM guide contradicts itself on this mapping (table 4-5 against table 4-6); go by the event names, which match this wiring.
      • GPIO3 event = Fault_Input_Event (33) on net SBU_FLT (item 36). GPIO0–2 and GPIO11 stay inputs: they are tied to GND.
      • Enable the Liquid Detection Configuration register (0x98): liquid detection and corrosion mitigation, ADC thresholds per TI's guidance, sample and wait times.
      • Disable BC1.2 and leave GPIO4/5 as ADC inputs.
      • Unmask the Liquid Detection event so the MCU can report it.
    • Parts: all JLC basic except U405. ERC is unchanged apart from four fewer GPIO-to-GND pin-type warnings. Layout: to be placed in the board redo; place_parts.py no longer places D403.

36. Schematic review 3 changes (2026-10-14, both ports). Review: ../../docs/devboard/schematic-review-3-2026-10-14.md.

    • H1, U405 FLT → TPS25751 GPIO3 (net SBU_FLT), R441 100k pull-up to LDO_3V3.
      • Why: a VBUS-to-SBU short makes the TPD2S300 open its switch, so the ADC sees only Rup/Rdown, reads "dry" and leaves VBUS on. With FLT on a fault input the port enters Type-C error recovery and VBUS turns off, as on TI's TPS25751EVM (SLVUCP9 §4.4, which uses GPIO2).
      • GPIO3 came off the GPIO0–3 GND tie. GPIO3 was used rather than GPIO2 because it is the end of the tie bar, so the label stays clear of it.
      • Configuration: GPIO3 = Fault_Input_Event (33).
    • H2, R442/R443 100k: R442 pulls LIQ_PU up to LDO_3V3 and R443 pulls LIQ_PD down to GND. Both hold the liquid-detect FETs off while GPIO6/7 are Hi-Z (from reset until the configuration loads), as TI's EVM does with R105/R110.
    • H3, BQ25756 tuning parts (TI EVM SLUUCT7 fig. 3-1):
      • R444–R447 0 Ω in the gate lines. The controller-side nets are named after the pins (HIDRV1, LODRV1, HIDRV2, LODRV2); the FET-side nets keep HG1/LG1/HG2/LG2.
      • R448/R449 0 Ω in the BTST lines (BTST1 → BTST1_C at C412/D404, BTST2 → BTST2_C at C413/D405).
      • DNP RC snubbers R450/C454 on SW1 and R451/C455 on SW2 (3.3 Ω 0805 + 33 pF C0G, the EVM placeholders).
      • All are drawn in a "GATE / BOOTSTRAP TUNING" block.
      • Layout: each 0 Ω sits right at its FET gate or BTST pin, so a few ohms can go in if the edges ring.
    • H4, U401/U501 symbol: now MonolithDev:TPS25751D, a copy of KiCad's stock symbol (made by tools/make_symbols.py) with GPIO11 typed bidirectional as the datasheet says. ERC is down to the 8 expected GPIO-to-GND warnings, with no errors.
    • Data flash and procedure (in ../../docs/devboard/bringup-config-checklist.md):
      • Min Blow Fuse Voltage = 10500 mV, because the WSFB1514 heater works only from 10.5–19.6 V.
      • COV Delay = 1 s, so the gauge acts before U102 (1–2 s) on a step overvoltage.
      • Never insert or remove a cell with USB or J104 power on (gauge sheet note 15).
    • Layout: new parts not placed yet (board redo). On the port sheet, the NOTES block moved under the tuning block.

37. Cost-down (2026-10-14). Details and datasheet checks: ../../docs/devboard/cost-down-2026-10-14.md.

    • Inductors:
      • L401/L501: Coilcraft XAL7030 → SMMS1040-2R2M (C149591, Isat 18 A, Irms 12 A, 9 mΩ) on KiCad's L_Changjiang_FXL1040 footprint, which is the same land as the datasheet's.
      • L402/L502 → APS0530M3R3H (C49073587), new footprint L_Coilank_APS0530 (tools/make_footprints.py section 15).
      • L201 → FNR4030S100MT (C167879).
    • Capacitors:
      • C431/C434/C435 (and 5xx): 47 µF 1210 → 22 µF 25 V 1206 (C12891, basic). The bank stays at about 114 µF effective; check their temperature in boost-mode charging.
      • C105/C206 → 2.2 µF 50 V X7R 1206 (C50254).
      • C406/C506 → 4.7 µF 50 V X7R 1206 (C29823).
    • U203: TPS70950 → HT7550-1 (C16106, SOT-89, Holtek pins 1 GND / 2 VIN / 3 VOUT). C204 is now 10 µF 50 V 1206 and C205 10 µF 25 V (Holtek basic circuit).
    • Same part number, JLC basic or preferred: D103 BZT52C15 (C19077412), D401/D501 SMAJ22A (C41376403), R410/R412 (and 5xx) 40.2k 0603 (C12447).
    • Q103: BSS138 → AO3400A (C20917, Vth max 1.45 V).
    • D301: out of stock → red KT-0603R (C2286, about 4 mA through R306).
    • R431/R531: the 2512 0R became a two-bar bridged solder jumper (cut to isolate the TPS62933).
    • Test points: 34 loops became bare 1.5 mm pads. Loops stay on GND (TP109, TP203, TP208, TP209, TP309, TP412, TP512), OUT_LO/OUT_HI (TP201/TP202) and SW1/SW2 (TP405/406, TP505/506).
    • Pin headers: hand-soldered (Sourcing property, out of the position file).
    • U301: bought outside JLC and consigned for placement (since rev A7 the CC2340R5MODA from TI.com; was the STM32WB1MMC from ST).
    • Costed BOM: bom_cost.csv, regenerated by tools/bom_cost.py [boards]. It prices every LCSC part at JLC's actual buy quantity, U301 at the ST price, and the hand-soldered headers from LCSC. U201 and J301 are left unpriced.
    • Result (5 boards): JLC parts $94.32 → $70.15 per board. With U301 from ST ($10.65 instead of JLC's $19.90) and 32 fee-bearing extended parts ($96 per order), that is about $80 per board, down from about $113.

38. Charger FETs: discrete PGQ04N070 (cost-down A16, 2026-10-14). Each charger leg was one IAUC45N04S6L063H half-bridge ($1.16, only 62 at JLC). Each is now two JinYu PGQ04N070 (C49384056, $0.12, PDFN3333 on AGM_PDFN-8_3.3x3.3mm_P0.65mm): Q401/Q407 on the USB side (SW1), Q402/Q408 on the battery side (SW2), and the 5xx twins.

    • Ratings: 40 V, 10 mΩ max at 4.5 V (IAUC45: 8.5 mΩ), Qg 14.7 nC.
    • Matches the production plan: the production BOM already calls for four discrete 40 V logic-level 3.3 × 3.3 mm FETs per port.
    • Symbol: new PGQ04N070 in tools/make_symbols.py.
    • Layout (board redo): the hot-loop rule above still applies, with each 0603 HF cap (C430/C438) now spanning the high-side drain and the low-side source of the pair. Keep each pair and its MLCCs tight.
    • Saving: $3.60 per board; the costed BOM is now about $77 per board (5 boards).
    • Bring-up: measure the FET temperatures and SW1/SW2 ringing; R444–R449 and the DNP snubbers are there to tune it.
    • Review 4: losses are about 1–1.6 W per FET at 100 W reverse from a 12 V pack, not 0.5 W (B-2). The high sides held on at 100 % duty run from the BQ25756's internal charge pump, not REGN; their gate voltage is a bring-up test, with fallback parts named (B-1, bringup-config-checklist.md §5).

39. 6-layer 1.6 mm board, TPD4S201 and the 1.6 mm USB-C connector (2026-10-14).

    • Board: 6 layers, 1.6 mm, 2 oz outer / 0.5 oz inner, vias epoxy-filled and capped. JLC's standard 0.3 mm / 0.45 mm via is the minimum. Stack-up, layer table, rules and net classes come from tools/setup_board.py, which now always rewrites the stack-up and keeps net classes it doesn't manage (Kelvin).
    • U405/U505 → TPD4S201TRGRRQ1 (TPD4S201-Q1, VQFN-20 RGR 3.5 × 3.5 mm, C49305973, $2.03, 128 in stock), wired as TI's TPS25751EVM fig. 5-5. It replaces the TPD2S300, whose centre ball needed a 0.15 mm via-in-pad.
      • CC and SBU both pass through it. The connector-side nets are C_CC1/C_CC2 and SBU1/SBU2; the controller side is CC1/CC2 (C401/C402, U401) and SBU1_SNS/SBU2_SNS (GPIO4/5).
      • RPD_G1/RPD_G2 tie to C_CC1/C_CC2, so its dead-battery Rd is present: this is a dual-role port that must charge a dead pack.
      • VPWR on LDO_3V3 with 1 µF (C452), VBIAS 0.1 µF 50 V (C451), FLT → GPIO3 (SBU_FLT, R441).
      • Footprint TI_RGR0020C_VQFN-20-1EP_3.5x3.5mm_P0.5mm_EP2.05mm from the datasheet land pattern (pads 0.6 × 0.24 at ±1.65 mm, 2.05 mm exposed pad, four 0.3 mm vias). New symbol TPD4S201.
    • D402/D502 (ESD2CAN24 on CC) removed: the TPD4S201 has IEC ESD and ±35 V surge protection on CC and SBU, and TI's EVM has no separate CC ESD.
    • J401/J501 → TYPE-C 16PCB1.6 IP68 (C55629729, $0.97, 695 in stock): the same land pattern and notch as the 0.8 mm part. New footprint name and 3D model (tools/make_3d_usbc.py 1.6).
    • TPS25751 exposed-pad thermal vias: 0.2 → 0.3 mm drill in the same 0.5 mm pads.
    • Board file: reset_board.py (new REF,... force-reload option) reloaded the changed footprints and removed D402/D502 and C453/C553. Parity: 0 issues.
    • Open: the BQ25756 footprint (U403/U503) shows a library-mismatch warning since the 6-layer change, although it was reloaded from the library. Check it with KiCad's "Compare Footprint with Library" during layout.

40. Rev A7: CC2340R5MODA MCU, TMP1075 board sensors, one IRQ line (2026-10-14). Plan and pin budget: ../../docs/devboard/cc2340-pin-budget.md. Applied by tools/mcu_cc2340.py (one-shot, from the rev A6 sheets).

    • U301 → TI CC2340R5MODA (BLE-only module, 512 kB flash / 64 kB RAM, on-chip OTA updates), replacing the STM32WB1MMC ($19.90, 0 at JLC). New symbol and footprint TI_MHA0024A_CC2340R5MODA_7x10mm (SWRS349A p.63-64). The footprint carries the fig. 9-2 antenna keep-out as two rule areas.

    • Wiring per SWRS349A fig. 9-1:

      • RFIO → C313 15 pF (CA1) → R321 0R (Z61) → ANT_IN. C314 (Z60) is DNP and C315 (Z62) is 1 pF, the LaunchPad values; retune them on the real board.
      • RSTN: R302 is now a 100k pull-up (was the BOOT0 pull-down) with C304. R303 and TP306 are removed.
      • No 32 kHz crystal: the firmware uses LFOSC.

    • Pins: 12 DIOs, 2 of them SWD, so 10 for the board, and only 4 analog. The new map has no spare pins:

      DIO	Signal
      DIO6 / DIO8	SCL / SDA
      DIO18 / DIO20	UART TX / RX
      DIO12	LED
      DIO24	CHG_INH
      DIO3 / DIO4	EN_5V1 / EN_5V2
      DIO21	3V3_SLEEP
      DIO11	IRQ_N

    • Board NTCs → TMP1075 on I2C.

      • Fitted: U302 port 1 stage (0x48), U303 port 2 stage (0x49), U304 between the connectors (0x4A).
      • DNP: U305 at the heatsink spot (0x4B), U306 at the protection FETs (0x4C).
      • Each has 0.1 µF (C308–C312, refs reused).
      • Removed: TH301–TH305, R308–R311, R320, NTC_EN and R316.
      • FET over-temperature now comes from the gauge's internal sensor; U306 is the fallback.

    • IRQ_N: the two TPS25751 IRQs, the gauge BTP (Q103) and the TMP1075 ALERTs share one open-drain net, replacing IRQ1/IRQ2/GAUGE_BTP.

      • R314 is the only pull-up; R315 and R114 are DNP. TP305 is removed.
      • J303 pin 2 now probes IRQ_N; pin 3 is unconnected.

    • R313 fitted at 470k (was DNP 100k). CC2340 pins float in reset, and the TPS62177's 1.4 µA SLEEP pull-down would otherwise put 3V3 in sleep mode (15 mA max) during boot. This costs 7 µA in S2.

    • Not done yet:

      • U301 has no LCSC number by design: TI.com, consigned (its Sourcing property says so since rev A8). In stock at TI.com when logged in (2026-10-15).
      • mcu-io-power-states.md and the bring-up checklist were rewritten for the CC2340 in rev A8 (item 42).
      • The STM32 notes in items 7, 10, 23 and 28 above are history.

41. Rev A8: review 4 pre-routing hardware fixes (2026-10-14). From ../../docs/devboard/schematic-review-4-2026-10-14.md. Applied by tools/review4_fixes.py (one-shot, from the rev A7 sheets). Part numbers checked against JLC's parts API the same day.

    Review item	Change	Part (LCSC)
    A-1b	R313 470k → 220k: 3V3_SLEEP reads about 0.92 × VDDS in reset instead of 0.83 (VIH 0.8). 15 µA while firmware holds SLEEP low	0603WAF2203T5E (C22961, basic)
    A-5	R314 100k → 47k (IRQ_N pull-up)	0603WAF4702T5E (C25819)
    A-6	R304/R305 4.7k → 3.3k (SCL/SDA rise time; run the bus at 100 kHz)	0603WAF3301T5E (C22978)
    A-7	R324 1k in series with J303 pin 2 (IRQ_N probe)	0603WAF1001T5E (C21190)
    A-9	R322/R323 1k in series with J302 TX/RX. Connect a USB-UART adapter only with 3V3 up	0603WAF1001T5E (C21190)
    A-10	C314 (Z60) placeholder 1p C0G, still DNP	GRM1555C1H1R0BA01D (C76952)
    B-3	R450/R451 (and 5xx) DNP snubber resistors 0805 → 1206 anti-surge 0.66 W. A 2010 or 0612 doesn't fit between Q401/Q408 and C443	ERJ-P08J3R3V (C3998398, 0 stock; DNP)
    C-3	C401/C402 (CC caps) 330p → 220p C0G	CL05C221JB5NNNC (C307445)
    C-4	D401/D501 SMAJ22A → TVS2200DRVR flat clamp (28 V at 40 A 8/20 µs). Stock KiCad symbol Power_Protection:TVS2200DRV and footprint WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm (TI DRV0006A pinout and 1.0 × 1.6 mm pad; KiCad's lands are 0.375 × 0.4 mm against TI's 0.3 × 0.45). Datasheet: ../datasheets/tvs2200.pdf	TVS2200DRVR (C523793, about 2.8k stock)
    C-8	TP415–TP421 (and 5xx), 1 mm pads: CC1, CC2, SBU_FLT, SBU1_SNS, SBU2_SNS, LIQ_PU, LIQ_PD	TestPoint_Pad_D1.0mm

    • Placement (place_blocks.py):
      • R322/R323 sit under J302, and R324 under J303 pin 2 in the R317–R319 row.
      • TP415/TP416 sit under U401's CC pins, TP417–TP419 in a column beside J401, and TP420/TP421 by the liquid-detect gates. Port 2 is the same layout 36 mm down.
      • R450/R451 are back in the snubber row.
      • D401/D501 stay at the SMAJ22A's spot.
    • Checks: ERC shows the 8 known warnings only; check_overlaps.py finds 0 text overlaps; board DRC shows 0 parity issues and no courtyard overlaps.
    • Not done (review 4):
      • A-2: the EV2400 procedure in checklist §2 step 4 and R312's Notes. D-5's J104 clamp (optional).
      • The documentation items: stale Notes and sheet text, the top-sheet revision log, power-budget.md, circuit-description.md and the checklist's STM32 sections.
      • BOM fields: 28 parts without an MPN; U301/J301 LCSC.

42. Rev A8, part 2: review 4 documentation, BOM and procedure items closed (2026-10-14). Schematic edits by tools/review4_docs.py (one-shot, after review4_fixes.py; shared helpers in tools/sch_edit.py).

    • A-2 (the last major): EV2400 work only with 3V3 up (J104 powered) and U301 held in reset. Rewritten in the bring-up checklist §2, R312/R301 Notes and MCU sheet note 10; nothing feeds TP308 with 3V3 down any more.
    • D-5: D105 SMAJ18A (Littelfuse, C148219) from the J104 side of D104 to GND: a bench supply left above about 22 V is clamped before the 25 V parts on PACK_P. On the header side it draws nothing from the pack. J104 moved right on the sheet; on the board D104 moved one body width left and D105 took its spot.
    • Schematic text:
      • Notes rewritten on R301, R302, R312, R315, R319, R321, Q103, R117, J102, RS101, R417/R517, R435/R535, R441/R541, C451/C551, C431/C434/C435 (and 5xx), R444–R449 (they named the wrong FETs since item 38), L401 and L402.
      • TP107 value IRQ_N; R127 value "0R".
      • Sheet notes: gauge 8 and 11, power 6, 8 and 10, USB 11, MCU 10; heading "I2C0 + IRQ PULL-UPS".
      • Sheet 4 renamed MCU and Sensors (nets on that sheet are now /MCU and Sensors/…); top-sheet address note names the CC2340 I2C0 and the TMP1075 addresses.
      • Revision log entries A7 and A8; every title block is A8.
    • BOM (D-11): MPN added on BT101–BT104, D101, Q101/Q102, U101, U204, RS101, C403–C405, R418/R419/R434 and U401–U404 (and 5xx). Sourcing on U301 (TI.com, consigned) and J301 (hand-fit; Samtec to be replaced by an unkeyed header JLC stocks). J301 is out of the position file.
    • Documents rewritten for the CC2340 and rev A8: bringup-config-checklist.md (with every review 4 CONFIG item: CCFG bootloader pin, IRQ_N rules, TMP1075 modes, I2C 100 kHz and bus clear, EN_5Vx first after reset, [NR] and Latch Limits, BTP_POL, [XL], EN_JEITA = 0, IBAT_REV interim, Q12/Q13, liquid-detect thresholds, INT_EVENT1 clear), mcu-io-power-states.md, power-budget.md (idle about 230–240 µA). Corrections in circuit-description.md §7–8, cost-down-2026-10-14.md (A3, A16) and cc2340-pin-budget.md.
    • Checks: ERC shows the 8 known warnings only; 0 text overlaps; board DRC shows 0 parity issues and no courtyard overlaps (429 parts).
    • Not closed by design: J301's replacement part (open, see its Sourcing); the bench measurements listed in the checklist §5. The ship-mode SOC threshold is 5 % (decided 2026-10-15).

43. C432/C532 → hybrid polymer (2026-10-15). The battery-side bulk is the only bulk capacitor biased while the board idles (from PACK_P whenever the gauge FETs are on). Its leakage is therefore idle drain, and the JIERR MA25V100M6x6 solid polymer was specified at 0.2CV = 500 µA max each (review 4 B-4).

    • Now: Panasonic EEH-ZA1E101XP (ZA hybrid: conductive polymer plus liquid electrolyte, C264047, $0.81, about 1.9k in stock). 100 µF 25 V, 30 mΩ, 2 A at 100 kHz, 10,000 h at 105 °C. Leakage ≤ 0.01CV = 25 µA.
    • Footprint: CP_Elec_6.3x7.7 (same pads as the 6.3 × 5.8; the can is taller).
    • Cost: +$0.64 per port, +$1.28 per board. Both parts are JLC extended, so the fee count doesn't change.
    • Options rejected:
      • Plain aluminium electrolytic: the same 0.01CV leakage limit and about $0.03–0.14, but 0.3–1 Ω ESR leaves only the MLCCs working at 600 kHz.
      • All-MLCC: about 13 × 1210 to reach 80 µF effective at 16.8 V, about $3.50 per port.
    • Kept: the solid polymers that are biased only while a port is active (USB side C421/C521, PP5V C443/C543); their leakage doesn't reach the idle budget.
    • Checks: ERC unchanged (the 8 known warnings); board DRC shows 0 parity issues and no courtyard overlaps. The taller can's reference text adds 6 silkscreen overlaps for the silkscreen pass.

44. Fewer JLC extended parts for a 2-board build (2026-10-15). JLC charges $3 per unique extended part per order, so at 2 boards each costs $1.50 per board. Applied by tools/bom_fee_cut.py; 37 → 27 extended parts, $124.28 → $108.49 per board at 2 boards.

    • Swapped to JLC basic/preferred parts (no footprint changes):
      • C313 15p → 0402CG150J500NT (C1548, C0G); C315 (and DNP C314) 1p → 0402CG1R0C500NT (C1550, C0G).
      • C401/C402 220p C0G → 0402B221K500NT (C1530, X7R).
      • R433/R434 107k/20.0k 0.1 % → 120k (C17436) / 22k (C17560) 1 %: PP5V 5.16 V instead of 5.08 V, inside the TPS25751's 4.9–5.5 V range.
      • C443/C543 220 µF 16 V polymer → 100 µF 35 V Honor HV1V107M0607PZ, the part C421 already uses (≈136 µF on PP5V against PD's 120 µF).
    • Hand-fit (bought from LCSC, soldered by hand, out of the position file): BT101–BT104, the 13 Harwin test loops, U202 and D105. All are dev-only and easy to hand-solder.
    • Kept as extended (no basic part fits): the ICs, FETs, inductors, USB-C connectors, sense resistors, polymer/hybrid bulk, TVS2200, LRB520S bootstrap diodes (the basic Schottkys leak 100–500× more), the 0.1 % charger FB divider (sets charge voltage) and R409 137k (ACOV).
    • Board fields refreshed by netlist_to_board.py only (no placement changes); DRC parity 0. ERC unchanged.

45. Smaller passives (2026-10-16). Each resistor and capacitor moves to the smallest package that keeps its rating, with two rules: nothing smaller than 0402, and no JLC basic part becomes extended. 160 parts change footprint (113 symbols; the port sheet counts twice). Applied by tools/downsize_passives.py (one-shot). The netlist connectivity is unchanged, ERC is unchanged (8), extended parts stay at 27, and the cost is $108.49 → $107.93 per board at 2 boards. Part classes and MPNs were checked against JLC's parts API the same day.

    • 0603 → 0402, all basic:

      Group	Part	Notes
      42 × 0.1 µF 50 V	C307331	Same rating. C430/C438 (hot-loop HF) get lower ESL at 0402.
      C450/C550 10 nF	C15195
      C452/C552 1 µF	C52923, 25 V	LDO_3V3 rail
      C405/C505 10 µF	C15525, 6.3 V	LDO_1V5 rail
      C301 4.7 µF	C23733, 10 V	3V3_MCU; about half the capacitance remains at 3.3 V

      Every basic resistor value with a basic 0402 part (UNI-ROYAL 0402WGF) moves too: 0R, 10R, 49.9, 100, 330, 1k, 3.3k, 4.7k, 5.1k, 10k, 22k, 47k, 51k, 100k and 1M. That includes R411/R511 10k and R434/R534 22k (both from 0805). The 0R parts that move are R1–R4, R202, R203, R307, R312 and R440/R540. The 10R parts that move are R425/R426/R428/R429 (the sense filters) and their port 2 copies.

    • One size down, basic:

      • C205, C403/C404 and their port 2 copies, 10 µF 25 V: 0805 → 0603 (C96446).
      • C409/C509 1 µF 50 V on PPHV: 0805 → 0603 (C15849, X5R).
      • C410/C411 and their port 2 copies on REGN/DRV_SUP: 0805 → 0603 4.7 µF 16 V (C19666).
      • C105 (PBI) and C206 (PACK_LP), 2.2 µF 50 V: 1206 → 0805 (C377773, X5R).
      • C204 (LDO_IN), 10 µF 50 V: 1206 → 0805 (GRM21BR61H106KE43L, C440198).
      • R433/R533 120k: 0805 preferred → 0603 basic (C25808).

    • Extended parts kept extended:

      • R418/R419 and their port 2 copies, the 0.1 % FB divider: 0805 → 0402 Panasonic ERA2AEB104X/103X (C445619/C191915). Both now come from one series, 0.1 % and 25 ppm/°C, so the ratio tracks.
      • R409/R509 137k: → 0402 (C32298).

    • Kept as they were, and why:

      • 0402 would turn these basic parts extended: 1.8k, 3.6k, 5.6k, 9.1k, 220k, 470k, 10M, R410/R412 40.2k (preferred), C414/C417 0.47 µF and C439/C539 33 nF.
      • 0402 derates too far: C407/C507 (10 µF on PP5V) and C207 22 µF (TPS62177 output; the only basic 0603 is 6.3 V).
      • No basic part in a smaller case: C406/C506 (4.7 µF 50 V on VBUS). C444/C445 and their port 2 copies (5 V buck input at about 17 V) stay 1206 to keep effective capacitance and ripple rating.
      • Kept large for function or rework: R101–R104 and R201 (they carry current), R420/R520 (gate-drive supply), the gate/BTST 0R tuning links R444–R449 and their port 2 copies, the 0805 rail links R207/R301/R401/R501, the shunts, the 1206/1210 bulk caps and the electrolytics.

    • Board: not updated yet. Run Tools → Update PCB from Schematic. That replaces the footprints in place, but the pads of parts already routed will no longer meet their traces.

46. Net tie R430/R530 removed (2026-10-16). It only kept VBAT_SYS and PACK_P as separate net names, which made routing the battery-side power path harder. Each charger's battery side is now PACK_P directly. In usb_port.kicad_sch, R430 became a wire, and the two VBAT_SYS labels became PACK_P power symbols (#PWR610/#PWR611, port 2 #PWR612/#PWR613). The */VBAT_SYS HighCurrent pattern was dropped from the project, since PACK_P is already HighCurrent. Netlist: R427/R527, R418/R518 and R429/R529 move to PACK_P, with no other change; ERC unchanged (8). The tie was out of the BOM, so cost is unchanged.

    • Routing rule now held by hand, not by DRC: take the SRN filter (R429) and the top of the FB divider (R418) from R427's PACK_P pad, not from the pour. A tap elsewhere on the 9.5 A bus adds the bus drop to the current reading and the charge voltage. Noted on the sheet beside the old R430 position.
    • Board: not updated. Update PCB from Schematic removes the two bridges and renames VBAT_SYS copper to PACK_P.

47. Charger gate resistors 10 Ω with turn-off diodes (2026-10-17, both ports). R444–R447 (R544–R547) went from 0 Ω to 10 Ω (C22859, 0603), to slow the switching edges. A BAT54WS (C7502694, SOD-323, the same part as D101, so no new JLC fee) sits across each: D406–D409 (D506–D509), cathode on the BQ25756 driver pin and anode on the FET gate. Turn-on goes through the 10 Ω; turn-off bypasses it through the diode, so the 45 ns dead time is kept (above 4.7 Ω without a diode, turn-off would eat it). The resistors' Notes named the wrong drivers and were rewritten. Applied by tools/gate_diodes.py (schematic) and tools/add_gate_diodes_board.py (board); the 8 diodes wait in a row below the board (y = 171 mm) for hand placement next to their resistors. Note: this makes review 4's B-1 (high-side gate drive margin) no better; check the gate waveforms at bring-up.

48. TMP1075 board sensors removed (2026-10-17, rev A8). U302–U306 and C308–C312 are gone from the MCU sheet and the board (they were parked off-board, unrouted). Board temperature now comes from parts already there (../../docs/devboard/circuit-description.md §6):

    • Cells and protection FETs: the gauge's DAStatus2 (MAC 0x0072, readable sealed) returns TS1–TS4, cell temperature, FET temperature and the gauge die.
    • Charger stages: each BQ25756's TS NTC (TH401/TH501), REG0x37/0x38 TS_ADC, read through the TPS25751 I2Cr 4CC task on its I2Cc bus. The chargers' warm/hot limits (74 / 94.5 °C) act in charge and reverse mode without firmware.
    • Not covered: the USB-C receptacles.
    • IRQ_N now has three sources (2 × TPS25751, gauge BTP). Saves 3 × TMP1075 + caps and one JLC extended part. Applied by tools/remove_tmp1075.py; docs, bom_cost.py, place_blocks.py and tidy_fields.py updated.

49. Routing finished (2026-10-17). Hand routing in KiCad did most of the board; the scripted finish pass (tools/finish_a_fixes.py … finish_h_fixes.py, one-shot, in order) did the rest, and a last hand round closed the remaining connections. Scripted: outline stray removed; all vias 0.45/0.3 mm; duplicate vias and zones removed; SDA/SCL and the CELL_N island taken off the In4 plane (CELL_N is a routed net, BT101− → RS101 is a 4 mm F.Cu pour); 34 parked parts placed (finish_c_place.py); 65 of 94 leftovers routed by the A* router route_signals6.py (In2 vertical / In3 horizontal, generated by make_router6.py); the two plane necks found by neck_bisect.py and nudged (finish_d_necks.py); two dangling-item and wedge clean-ups (finish_f_cleanup.py, finish_g_fixes.py, finish_h_fixes.py). A GND reference-via sprinkle (finish_d_gndvias.py) was rejected because it cut the power pours and was stripped again; don't repeat it. Silkscreen by finish_e_silk.py (re-runnable): refs only on J/JP/BT, abbreviated test-point net labels at 0.8 mm, header pin labels, section titles, board name and "FIT CELLS BEFORE USB"; 19 test-point labels in the 2.54 mm loop grids found no room and are not printed (TP402/404/407–409/418/421, TP509/510/512/513/518/519, TP104/107/201; J104/J301 refs). State: DRC 0 unconnected, 0 errors other than the known lib-footprint mismatches (U403/U503 known; U301/U404/U504 are silk trims on the board instances). check_routing_rules.py notes, left as they are: 563 In2/In3 direction deviations and eight segments on the In4 plane (port 1/2 SBU_FLT, SCL) from hand routing; 44 via rows under 0.3 mm plane webs (the 9-via stitch rows under SW1/SW2 and the RAC corridor are the ones that matter); 156 signal vias without a GND via within 1 mm. Known layout weakness for rev 2: each BQ25756 (U403/U503) sits 15–34 mm from its FET gates with 0.2 mm gate tracks (TI: ≥ 0.5 mm, short); the 5 V buck sits in between. Move the controller next to the FET block next revision.

50. Fab outputs (2026-10-17). tools/export_fab.py (re-runnable) refills the zones, plots gerbers with JLC's KiCad settings (Protel extensions, soldermask subtracted from silk, no X2/netlist attributes) plus Excellon drills (mm, PTH/NPTH separate, Gerber X2 maps) into fab/gerbers/ and fab/MonolithDev-gerbers.zip, and writes the JLC assembly files: fab/MonolithDev-bom.csv (Comment, Designator, Footprint, LCSC Part #; 85 lines) and fab/MonolithDev-cpl.csv (Designator, Mid X, Mid Y, Layer, Rotation; 317 parts, all top side). fab/MonolithDev-hand-fit.csv lists the 51 parts kept out of the JLC files and why: the 17 DNP parts, the hand-fit parts (holders, headers, the 1.5 mm probe pads, U201/U202, D105) and U301 (CC2340R5MODA, bought from TI, no LCSC number). Check the rotations in JLC's placement preview before confirming an order; KiCad and JLC disagree on the zero angle for some packages. Not ordered yet: the TI board is tested first.

Open items (defaults I picked; confirm or change)

Moot since the board was not built; they are kept as history. P0's open items are in ../Production/README.md.

Changes planned for the next board revision are listed in ../../docs/devboard/rev2-changes.md.

• Optional gauge-BAT INA190 dropped (2026-10-13): not needed. With the pack on battery only, the gauge's whole supply current flows through R105 (100 Ω, TI's BAT network D101 → R105 → BAT): 50–340 µA reads as 5–34 mV across R105 on a multimeter.
• STM32WB1MMC antenna keep-out (rev A6; the CC2340R5MODA footprint carries TI's keep-out, item 40): ST publishes no keep-out drawing for the module (DS14096 has none; ST community threads confirm). The board follows ST's reference PCB: module at the top edge, antenna (pin-1) end 0.5 mm from it. Rev A5 had a rule area ANT_KEEPOUT (place_parts.py) banning tracks, vias and pours on all copper layers in the strip either side of and above the module (x 141–159, y 0–4.2 mm). The layout reset removed it. Rev A7: not re-added. TI wants ground on both sides of the CC2340 antenna, and the footprint carries the keep-out under it (Board, rev A7 update). Check BLE range at bring-up.
• Pin map (rev A6, STM32; rev A7 map in item 40) checked against the STM32WB15 datasheet (DS13258 table 15): ADC1_IN6/8/9/10 on PA1/PA3/PA4/PA5, WKUP1/WKUP4 on PA0/PA2, I2C1 on PB6/PB7, USART1 on PA9/PA10, SWD on PA13/PA14. A final pass in STM32CubeMX when the firmware project is set up is still worthwhile (it also catches clock-tree and peripheral conflicts).

Footprints

MonolithDev.pretty holds the footprints KiCad doesn't ship, generated by tools/make_footprints.py from the datasheets in ../../datasheets/ (2026-10-11). Every symbol pin has a pad and every numbered pad a pin (checked against the netlist).

Regenerating symbols

python tools/make_symbols.py

Then in KiCad, Tools → Update Symbols from Library (or the MCP update_symbol_from_library).