Teresina Rack

Teresina-Rack

Version 0.1.0-alpha0 — under engineering review; not fabricated or hardware-tested. The current PCB is a 12-layer baseline with confirmed electrical, BOM, package and layout findings. It is not approved for production.

The goal is an open, self-fabricatable Daisy Patch SM-compatible Eurorack submodule: the same carrier interface and libDaisy application compatibility through a small Teresina firmware variant. Source compatibility and hardware behavior remain qualification targets. See the firmware policy and production review.

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Production target

4 copper layers preferred; 6 acceptable if required; 8 the final fallback. Evaluate in that order with new placement, BGA escape, timing, return-path and manufacturer review. Document the constraint and alternatives tried before increasing layer count. Twelve layers describe the existing file only and are outside the redesign target. See the redesign plan.

Disposable four-layer MCU escape trials reached zero native clearance errors when six power-pad vias were filled/capped. The full board remains unrouted in those studies, and SDRAM escape at the inherited placement still fails. These results do not qualify a four-layer production design.

Existing hardware

Manufacturer pin maps confirm the core/codec/analog signal assignments. 74 checked digital-net assignments agree with pinned libDaisy. Complete carrier fit, sequencing, analog performance and firmware execution still need first-article validation.

Open compatibility findings

Official libDaisy v9.0.0 is the pinned firmware reference. Its stock refresh sweep is 168.35 ms against the proposed ISSI part's 64 ms requirement. An opt-in Teresina prototype now implements a conservative refresh profile and reviewed clock/init changes. Crossbuilds support a limited source-compatibility claim; stock binaries are unsupported and hardware tests remain unrun. See the firmware decision and original retention check.

An expanded memory-replacement search found no datasheet-backed fix for unchanged firmware. Etron EM63B325BK is an unresolved catalogue lead; it has not been qualified or selected.

The review also confirms wrong ferrite/inductor/capacitor ordering data, crystal/diode footprint mismatches, CV amplifiers on the wrong supply, gate-output resistance differences and remote critical power/clock/decoupling loops. The earlier claims of an identical analog implementation and completed production validation are superseded by the current findings. Reviewed corrections are staged outside the checkout until the complete design can be synchronized.

Validation

A clean native DRC does not resolve wrong ordered parts or prove stock-firmware retention, thermal safety, analog performance or carrier fit. See the full review for passed, failed and unrun checks.

Development and fabrication

Use KiCad 10 for the project under TeresinaRack/. The configured cloud environment retains checksum-verified KiCad 10.0.7, ngspice 47, kicad-tools, KiCadRoutingTools and kicad-happy; reproducible setup/startup instructions are saved in environment settings. Interactive GUI editing and hardware programming were not validated in the headless environment.

Keep every routing operation's before/after evidence and run native DRC/refill, independent connectivity and copper hygiene before accepting it. Use the actual selected JLCPCB process, not an unrelated generic profile. Final fabrication requires an accepted stackup, explicit filled/capped-via process, corrected sourcing-complete BOM, CPL/assembly drawings, header dimensions and first-article plan. The current files and exports are not an approved order package.

kicad-cli pcb drc --format json -o drc.json TeresinaRack.kicad_pcb
kicad-cli sch erc --format json -o erc.json TeresinaRack.kicad_sch

Run from TeresinaRack/ and inspect every report severity and unconnected item. Exit 0 alone does not establish a pass. Generated fabrication files belong in the ignored fab/ directory.

Repository layout

• TeresinaRack/: editable KiCad project, custom symbols and rules.
• docs/production-review.md: current evidence, blockers and review limits.
• docs/redesign-plan.md: requirements, 4 → 6 → 8 sequence and acceptance gates.
• docs/review/: inventory, calculations and independent subsystem evidence.
• DESIGN.md: historical working notes, superseded by the current review.
• bom/: baseline BOM working files; not approved production sourcing.

Acknowledgements

• Electro-Smith — the Daisy platform, libDaisy, and the published Patch SM pinout/footprint that make a compatible open re-implementation possible.
• kicad-happy — schematic/PCB/EMC/SPICE analysis suite used for validation.

This is an independent DIY project, not affiliated with or endorsed by Electro-Smith. "Daisy" and "Patch SM" are their marks. Build at your own risk — check everything before powering your rack.