DRV8353FSRTAR

Texas InstrumentsExtended

Part id: ti/DRV8353FSRTAR
Category: Brushless DC (BLDC) Motor Driver
Package: WQFN-40-EP(6x6)
Pins: 41
In stock: 668 at JLCPCB (C1518717)
Used on: 5 open-source boards

Overview

The DRV8353FSRTAR is a brushless DC (BLDC) Motor Driver made by Texas Instruments in a WQFN-40-EP(6x6) package with 41 pins.

PCBKit's library has its KiCad symbol (EasyEDA_Cloud:DRV8353FSRTAR, from EasyEDA) and its footprint (EasyEDA_Cloud:WQFN-40_L6.0-W6.0-P0.50-TL-EP4.5, from EasyEDA), ready for a KiCad board. 668 are in stock at JLCPCB (part C1518717). 5 open-source boards in 5 repositories on GitHub use it.

Symbol

EasyEDA_Cloud:DRV8353FSRTARFrom EasyEDA

Footprint

EasyEDA_Cloud:WQFN-40_L6.0-W6.0-P0.50-TL-EP4.5From EasyEDA

From the datasheet

Supply, least: 9 V · VM, recommended operating min · p. 7
Supply, most: 75 V · VM, recommended operating max · p. 7
Supply, least: 7 V · VDRAIN, recommended operating min · p. 7
Supply, most: 100 V · VDRAIN, recommended operating max · p. 7
Supply, absolute maximum: 80 V · VM, absolute max · p. 6
Supply, absolute maximum: 102 V · VDRAIN, absolute max · p. 6
Works from: -40 °C · Operating ambient temperature min · p. 7
Works up to: 125 °C · Operating ambient temperature max · p. 7
Junction, hottest: 150 °C · Operating junction temperature max · p. 7
Takes working: 10.4 mA · sum of VM and VDRAIN typical operating currents, 48 V, ENABLE = 3.3 V, inputs low · p. 8
Takes asleep: 20 µA · Sleep supply current typical, 48 V, 25°C · p. 8
Junction to air (RTA (WQFN)): 26.1 K/W · Junction-to-ambient thermal resistance · p. 7
Junction to board (RTA (WQFN)): 8.4 K/W · Junction-to-board thermal resistance · p. 7
Junction to case (RTA (WQFN)): 13.1 K/W · Junction-to-case top thermal resistance · p. 7

What it is and has

Gate driver: Triple half-bridge, 9 to 100 V · p. 1
Functional safety: Quality-Managed · p. 1
Slew rate control: Adjustable for EMI performance · p. 1
Peak source gate current: 50 mA to 1 A · p. 1
Peak sink gate current: 100 mA to 2 A · p. 1
Current shunt amplifiers: 3 · p. 1
Current shunt amplifier gain: 5, 10, 20, 40 V/V · p. 1
Current sensing: Bidirectional or unidirectional · p. 1
PWM modes: 6x, 3x, 1x, independent · p. 1
Sensored operation: 120° · p. 1
Protection: VM undervoltage lockout · p. 1
Protection: Gate drive supply undervoltage · p. 1
Protection: MOSFET VDS overcurrent protection · p. 1
Protection: MOSFET shoot-through prevention · p. 1
Protection: Gate driver fault detection · p. 1
Protection: Thermal warning and shutdown · p. 1
Fault indication: nFAULT · p. 1
Gate driver: 9 to 100 V, triple half-bridge · p. 1
Gate drive: Smart gate drive architecture · p. 1

Specifications

193

Parameter	Conditions	As printed	Page
Power supply pin voltage (VM)	TA = –40°C to +125°C	min -0.3 · max 80 V	6
Voltage differential between ground pins (AGND, BGND, DGND, PGND)	TA = –40°C to +125°C	min -0.3 · max 0.3 V	6
MOSFET drain sense pin voltage (VDRAIN)	TA = –40°C to +125°C	min -0.3 · max 102 V	6
MOSFET drain sense pin voltage slew rate (VDRAIN)	TA = –40°C to +125°C	min 0 · max 2 V/us	6
Charge pump pin voltage (CPH, VCP)	Maximum = VVDRAIN + 16 V	min -0.3 V	6
Charge-pump negative-switching pin voltage (CPL)	Maximum = VVDRAIN	min -0.3 V	6
Low-side gate drive regulator pin voltage (VGLS)		min -0.3 · max 18 V	6
Internal logic regulator pin voltage (DVDD)		min -0.3 · max 5.75 V	6
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS)		min -0.3 · max 5.75 V	6
Continuous high-side gate drive pin voltage (GHx)	Maximum = VVCP + 0.3 V; minimum subject to footnote (2)	min -5 V	6
Transient 200-ns high-side gate drive pin voltage (GHx)	Maximum = VVCP + 0.3 V	min -10 V	6
High-side gate drive pin voltage with respect to SHx (GHx)		min -0.3 · max 16 V	6
Continuous high-side source sense pin voltage (SHx)	Minimum subject to footnote (2)	min -5 · max 102 V	6
Continuous high-side source sense pin voltage (SHx)	Maximum = VVDRAIN + 5 V; minimum subject to footnote (2)	min -5 V	6
Transient 200-ns high-side source sense pin voltage (SHx)	Maximum = VVDRAIN + 10 V	min -10 V	6
Continuous low-side gate drive pin voltage (GLx)	Maximum = VVGLS + 0.3 V	min -1 V	6
Transient 200-ns low-side gate drive pin voltage (GLx)	Maximum = VVGLS + 0.3 V	min -5 V	6
Continuous low-side source sense pin voltage (SLx)		min -1 · max 1 V	6
Transient 200-ns low-side source sense pin voltage (SLx)		min -5 · max 5 V	6
Continuous shunt amplifier input pin voltage (SNx, SPx)		min -1 · max 1 V	6
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)		min -5 · max 5 V	6
Reference input pin voltage (VREF)		min -0.3 · max 5.75 V	6
Shunt amplifier output pin voltage (SOx)	Maximum = VVREF + 0.3 V	min -0.3 V	6
Ambient temperature, TA TA		min -40 · max 125 °C	6
Junction temperature, TJ TJ		min -40 · max 150 °C	6
Storage temperature, Tstg Tstg		min -65 · max 150 °C	6
Electrostatic discharge V(ESD)	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; value ±1000 V	max 1000 V	6
Electrostatic discharge V(ESD)	Charged-device model (CDM), per JEDEC specification JESD22-C101; value ±500 V	max 500 V	6
Gate driver power supply voltage (VM) VVM		min 9 · max 75 V	7
Charge pump reference and drain voltage sense (VDRAIN) VVDRAIN		min 7 · max 100 V	7
Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) VI		min 0 · max 5.5 V	7
Applied PWM signal (INHx, INLx) fPWM	Power dissipation and thermal limits must be observed	min 0 · max 200 kHz	7
Switch-node slew rate range (SHx) tSH		min 0 · max 2 V/ns	7
High-side average gate-drive current (GHx) IGATE_HS	Power dissipation and thermal limits must be observed	min 0 · max 25 mA	7
Low-side average gate-drive current (GLx) IGATE_LS	Power dissipation and thermal limits must be observed	min 0 · max 25 mA	7
External load current (DVDD) IDVDD	Power dissipation and thermal limits must be observed	min 0 · max 10 mA	7
Reference voltage input (VREF) VVREF		min 3 · max 5.5 V	7
Shunt amplifier output current (SOx) ISO		min 0 · max 5 mA	7
Open drain pullup voltage (nFAULT, SDO) VOD		min 0 · max 5.5 V	7
Open drain output current (nFAULT, SDO) IOD		min 0 · max 5 mA	7
Operating ambient temperature TA		min -40 · max 125 °C	7
Operating junction temperature TJ		min -40 · max 150 °C	7
Junction-to-ambient thermal resistance RθJA	DRV8353F, RTA (WQFN), 40 PINS	typ 26.1 °C/W	7
Junction-to-case (top) thermal resistance RθJC(top)	DRV8353F, RTA (WQFN), 40 PINS	typ 13.1 °C/W	7
Junction-to-board thermal resistance RθJB	DRV8353F, RTA (WQFN), 40 PINS	typ 8.4 °C/W	7
Junction-to-top characterization parameter ψJT	DRV8353F, RTA (WQFN), 40 PINS	typ 0.1 °C/W	7
Junction-to-board characterization parameter ψJB	DRV8353F, RTA (WQFN), 40 PINS	typ 8.4 °C/W	7
Junction-to-case (bottom) thermal resistance RθJC(bot)	DRV8353F, RTA (WQFN), 40 PINS	typ 1.1 °C/W	7
VM operating supply current IVM	VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V	typ 8.5 · max 13 mA	8
VDRAIN operating supply current IVDRAIN	VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V	typ 1.9 · max 4 mA	8
Sleep mode supply current ISLEEP	ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C	typ 20 · max 40 uA	8
Sleep mode supply current ISLEEP	ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C	max 100 uA	8
Reset pulse time tRST	ENABLE = 0 V period to reset faults	min 5 · max 40 us	8
Turnon time tWAKE	VVM > VUVLO, ENABLE = 3.3 V to outputs ready	max 1 ms	8
Turnoff time tSLEEP	ENABLE = 0 V to device sleep mode	max 1 ms	8
DVDD regulator voltage VDVDD	IDVDD = 0 to 10 mA	min 4.75 · typ 5 · max 5.25 V	8
VCP operating voltage with respect to VDRAIN VVCP	VVM = 15 V, IVCP = 0 to 25 mA	min 9 · typ 10.5 · max 12 V	8
VCP operating voltage with respect to VDRAIN VVCP	VVM = 12 V, IVCP = 0 to 20 mA	min 7.5 · typ 10 · max 11.5 V	8
VCP operating voltage with respect to VDRAIN VVCP	VVM = 10 V, IVCP = 0 to 15 mA	min 6 · typ 8 · max 9.5 V	8
VCP operating voltage with respect to VDRAIN VVCP	VVM = 9 V, IVCP = 0 to 10 mA	min 5.5 · typ 7.5 · max 8.5 V	8
VGLS operating voltage with respect to GND VVGLS	VVM = 15 V, IVGLS = 0 to 25 mA	min 13 · typ 14.5 · max 16 V	8
VGLS operating voltage with respect to GND VVGLS	VVM = 12 V, IVGLS = 0 to 20 mA	min 10 · typ 11.5 · max 12.5 V	8
VGLS operating voltage with respect to GND VVGLS	VVM = 10 V, IVGLS = 0 to 15 mA	min 8 · typ 9.5 · max 10.5 V	9
VGLS operating voltage with respect to GND VVGLS	VVM = 9 V, IVGLS = 0 to 10 mA	min 7 · typ 8.5 · max 9.5 V	9
Input logic low voltage VIL	ENABLE, INHx, INLx, nSCS, SCLK, SDI	min 0 · max 0.8 V	9
Input logic high voltage VIH	ENABLE, INHx, INLx, nSCS, SCLK, SDI	min 1.5 · max 5.5 V	9
Input logic hysteresis VHYS	ENABLE, INHx, INLx, nSCS, SCLK, SDI	typ 100 mV	9
Input logic low current IIL	VVIN = 0 V	min -5 · max 5 uA	9
Input logic high current IIH	VVIN = 5 V	typ 50 · max 70 uA	9
Pulldown resistance RPD	Logic-level inputs; To GND	typ 100 kΩ	9
Propagation delay tPD	INHx/INLx transition to GHx/GLx transition	typ 200 ns	9
Output logic low voltage VOL	nFAULT, SDO; IO = 5 mA	max 0.125 V	9
Output high impedance leakage IOZ	nFAULT, SDO; VO = 5 V	min -2 · max 2 uA	9
High-side gate drive voltage with respect to SHx VGSH	VVM = 15 V, IVCP = 0 to 25 mA	min 9 · typ 10.5 · max 12 V	9
High-side gate drive voltage with respect to SHx VGSH	VVM = 12 , IVCP = 0 to 20 mA	min 7.5 · typ 10 · max 11.5 V	9
High-side gate drive voltage with respect to SHx VGSH	VVM = 10 V, IVCP = 0 to 15 mA	min 6 · typ 8 · max 9.5 V	9
High-side gate drive voltage with respect to SHx VGSH	VVM = 9 V, IVCP = 0 to 10 mA	min 5.5 · typ 7.5 · max 8.5 V	9
Low-side gate drive voltage with respect to PGND VGSL	VVM = 15 V, IVGLS = 0 to 25 mA	min 9.5 · typ 11 · max 12.5 V	9
Low-side gate drive voltage with respect to PGND VGSL	VVM = 12 V, IVGLS = 0 to 20 mA	min 9 · typ 10.5 · max 12 V	9
Low-side gate drive voltage with respect to PGND VGSL	VVM = 10 V, IVGLS = 0 to 15 mA	min 7.5 · typ 9 · max 10.5 V	9
Low-side gate drive voltage with respect to PGND VGSL	VVM = 9 V, IVGLS = 0 to 10 mA	min 6.5 · typ 8 · max 9.5 V	9
Gate drive dead time tDEAD	SPI Device; DEAD_TIME = 00b	typ 50 ns	10
Gate drive dead time tDEAD	SPI Device; DEAD_TIME = 01b	typ 100 ns	10
Gate drive dead time tDEAD	SPI Device; DEAD_TIME = 10b	typ 200 ns	10
Gate drive dead time tDEAD	SPI Device; DEAD_TIME = 11b	typ 400 ns	10
Peak current gate drive time tDRIVE	SPI Device; TDRIVE = 00b	typ 500 ns	10
Peak current gate drive time tDRIVE	SPI Device; TDRIVE = 01b	typ 1000 ns	10
Peak current gate drive time tDRIVE	SPI Device; TDRIVE = 10b	typ 2000 ns	10
Peak current gate drive time tDRIVE	SPI Device; TDRIVE = 11b	typ 4000 ns	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0000b	typ 50 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0001b	typ 50 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0010b	typ 100 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0011b	typ 150 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0100b	typ 300 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0101b	typ 350 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0110b	typ 400 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 0111b	typ 450 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1000b	typ 550 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1001b	typ 600 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1010b	typ 650 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1011b	typ 700 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1100b	typ 850 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1101b	typ 900 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1110b	typ 950 mA	10
Peak source gate current IDRIVEP	SPI Device; IDRIVEP_HS or IDRIVEP_LS = 1111b	typ 1000 mA	10
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0000b	typ 100 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0001b	typ 100 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0010b	typ 200 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0011b	typ 300 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0100b	typ 600 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0101b	typ 700 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0110b	typ 800 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 0111b	typ 900 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1000b	typ 1100 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1001b	typ 1200 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1010b	typ 1300 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1011b	typ 1400 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1100b	typ 1700 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1101b	typ 1800 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1110b	typ 1900 mA	11
Peak sink gate current IDRIVEN	SPI Device; IDRIVEN_HS or IDRIVEN_LS = 1111b	typ 2000 mA	11
Gate holding current IHOLD	Source current after tDRIVE	typ 50 mA	11
Gate holding current IHOLD	Sink current after tDRIVE	typ 100 mA	11
Gate strong pulldown current ISTRONG	GHx to SHx and GLx to SPx/SLx	typ 2 A	11
Gate hold off resistor ROFF	GHx to SHx and GLx to SPx/SLx	typ 150 kΩ	11
Amplifier gain GCSA	SPI Device; CSA_GAIN = 00b	min 4.85 · typ 5 · max 5.15 V/V	11
Amplifier gain GCSA	SPI Device; CSA_GAIN = 01b	min 9.7 · typ 10 · max 10.3 V/V	11
Amplifier gain GCSA	SPI Device; CSA_GAIN = 10b	min 19.4 · typ 20 · max 20.6 V/V	11
Amplifier gain GCSA	SPI Device; CSA_GAIN = 11b	min 38.8 · typ 40 · max 41.2 V/V	11
Settling time to ±1% tSET	VO_STEP = 0.5 V, GCSA = 5 V/V	typ 250 ns	11
Settling time to ±1% tSET	VO_STEP = 0.5 V, GCSA = 10 V/V	typ 500 ns	11
Settling time to ±1% tSET	VO_STEP = 0.5 V, GVSA = 20 V/V	typ 1000 ns	11
Settling time to ±1% tSET	VO_STEP = 0.5 V, GCSA = 40 V/V	typ 2000 ns	11
Common mode input range VCOM		min -0.15 · max 0.15 V	11
Differential mode input range VDIFF		min -0.3 · max 0.3 V	11
Input offset error VOFF	VSP = VSN = 0 V	min -3 · max 3 mV	11
Drift offset VDRIFT	VSP = VSN = 0 V	typ 10 uV/°C	11
SOx output voltage linear range VLINEAR	Maximum = VVREF – 0.25 V	min 0.25 V	11
SPx/SNx input bias current IBIAS		max 250 uA	12
SOx output slew rate VSLEW	60-pF load	typ 10 V/us	12
VREF input current IVREF	VVREF = 5 V	typ 1.5 · max 2.5 mA	12
Unity gain bandwidth UGB	DRV835xF: 60-pF load	typ 10 MHz	12
VM undervoltage lockout VVM_UV	DRV835xF: VM falling, UVLO report	min 8 · typ 8.3 · max 8.8 V	12
VM undervoltage lockout VVM_UV	DRV835xF: VM rising, UVLO recovery	min 8.2 · typ 8.5 · max 9 V	12
VM undervoltage hysteresis VVM_UVH	Rising to falling threshold	typ 200 mV	12
VM undervoltage deglitch time tVM_UVD	VM falling, UVLO report	typ 10 us	12
VDRAIN undervoltage lockout VVDR_UV	DRV835xF: VDRAIN falling, UVLO report	min 6.1 · typ 6.4 · max 6.8 V	12
VDRAIN undervoltage lockout VVDR_UV	DRV835xF: VDRAIN rising, UVLO recovery	min 6.3 · typ 6.6 · max 7 V	12
VDRAIN undervoltage hysteresis VVDR_UVH	Rising to falling threshold	typ 200 mV	12
VDRAIN undervoltage deglitch time tVDR_UVD	VDRAIN falling, UVLO report	typ 10 us	12
VGLS low-side regulator undervoltage lockout VVGLS_UV	VGLS falling, GDUV report	typ 4.25 V	12
High-side gate clamp VGS_CLAMP	Positive clamping voltage	min 12.5 · typ 13.5 · max 16 V	12
High-side gate clamp VGS_CLAMP	Negative clamping voltage	typ -0.7 V	12
VDS overcurrent trip voltage VVDS_OCP	SPI Device; DRV835xF: VDS_LVL = 0000b	min 0.041 · typ 0.06 · max 0.072 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; DRV835xF: VDS_LVL = 0001b	min 0.051 · typ 0.07 · max 0.084 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; DRV835xF: VDS_LVL = 0010b	min 0.061 · typ 0.08 · max 0.096 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; DRV835xF: VDS_LVL = 0011b	min 0.071 · typ 0.09 · max 0.108 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; DRV835xF: VDS_LVL = 0100b	min 0.081 · typ 0.1 · max 0.115 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 0101b	min 0.18 · typ 0.2 · max 0.22 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 0110b	min 0.27 · typ 0.3 · max 0.33 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 0111b	min 0.36 · typ 0.4 · max 0.44 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1000b	min 0.45 · typ 0.5 · max 0.55 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1001b	min 0.54 · typ 0.6 · max 0.66 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1010b	min 0.63 · typ 0.7 · max 0.77 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1011b	min 0.72 · typ 0.8 · max 0.88 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1100b	min 0.81 · typ 0.9 · max 0.99 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1101b	min 0.9 · typ 1 · max 1.1 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1110b	min 1.35 · typ 1.5 · max 1.65 V	13
VDS overcurrent trip voltage VVDS_OCP	SPI Device; VDS_LVL = 1111b	min 1.8 · typ 2 · max 2.2 V	13
VDS and VSENSE overcurrent deglitch time tOCP_DEG	SPI Device; OCP_DEG = 00b	typ 1 us	13
VDS and VSENSE overcurrent deglitch time tOCP_DEG	SPI Device; OCP_DEG = 01b	typ 2 us	13
VDS and VSENSE overcurrent deglitch time tOCP_DEG	SPI Device; OCP_DEG = 10b	typ 4 us	13
VDS and VSENSE overcurrent deglitch time tOCP_DEG	SPI Device; OCP_DEG = 11b	typ 8 us	13
VSENSE overcurrent trip voltage VSEN_OCP	SPI Device; SEN_LVL = 00b	typ 0.25 V	13
VSENSE overcurrent trip voltage VSEN_OCP	SPI Device; SEN_LVL = 01b	typ 0.5 V	13
VSENSE overcurrent trip voltage VSEN_OCP	SPI Device; SEN_LVL = 10b	typ 0.75 V	13
VSENSE overcurrent trip voltage VSEN_OCP	SPI Device; SEN_LVL = 11b	typ 1 V	13
Overcurrent retry time tRETRY	SPI Device; TRETRY = 0b	typ 8 ms	13
Overcurrent retry time tRETRY	SPI Device; TRETRY = 1b	typ 50 us	13
Thermal warning temperature TOTW	Die temperature, TJ	min 130 · typ 150 · max 170 °C	13
Thermal shutdown temperature TOTSD	Die temperature, TJ	min 150 · typ 170 · max 190 °C	13
Thermal hysteresis THYS	Die temperature, TJ	typ 20 °C	13
SPI ready after enable tREADY	VM > UVLO, ENABLE = 3.3 V	max 1 ms	14
SCLK minimum period tCLK		min 100 ns	14
SCLK minimum high time tCLKH		min 50 ns	14
SCLK minimum low time tCLKL		min 50 ns	14
SDI input data setup time tSU_SDI		min 20 ns	14
SDI input data hold time tH_SDI		min 30 ns	14
SDO output data delay time tD_SDO	SCLK high to SDO valid	max 30 ns	14
nSCS input setup time tSU_nSCS		min 50 ns	14
nSCS input hold time tH_nSCS		min 50 ns	14
nSCS minimum high time before active low tHI_nSCS		min 400 ns	14
nSCS disable time tDIS_nSCS	nSCS high to SDO high impedance; nominal value	typ 10 ns	14

Ordering codes, by the datasheet

DRV8353FSRTAR: WQFN (RTA) | 40 · 2000-unit LARGE T&R; operating temperature -40 to 125 °C · p. 73
DRV8353FSRTAR.A: WQFN (RTA) | 40 · 2000-unit LARGE T&R; NIPDAU lead finish; operating temperature -40 to 125 °C · p. 73
DRV8353FSRTARG4: WQFN (RTA) | 40 · 2000-unit LARGE T&R; NIPDAU lead finish; operating temperature -40 to 125 °C · p. 73
DRV8353FSRTARG4.A: WQFN (RTA) | 40 · 2000-unit LARGE T&R; NIPDAU lead finish; operating temperature -40 to 125 °C · p. 73

Parameters

Current - Output High(IOH): 1A
Current - Output Low(IOL): 2A
Current - Supply: 10.4mA
Driven Configuration: Three Phase
Features: Enable shutdown
Input Logic Level - High: 1.5V
Input Logic Level - Low: 800mV
Junction Temperature(Max): 150℃
Load Type: MOSFET
Number of Drivers: 3
Operating Temperature: -40℃~+125℃
Quiescent Current(Iq): 20uA
Standby Current: 20uA
Thermal Resistance(Junction to Ambient): 26.1℃/W
Thermal Resistance(Junction to Board): 8.4℃/W
Thermal Resistance(Junction to Case): 13.1℃/W
Voltage - Supply: 7V~100V
Voltage - Supply(Absolute Max): 80V

Order codes

DRV8353FSRTARLCSC C1518717

Pinout

The pins of the DRV8353FSRTAR
Pin	Name	Type
1	CPL	Unspecified
2	CPH	Unspecified
3	VM	Unspecified
4	VDRAIN	Unspecified
5	VCP	Unspecified
6	GHA	Unspecified
7	SHA	Unspecified
8	GLA	Unspecified
9	SPA	Unspecified
10	SNA	Unspecified
11	SNB	Unspecified
12	SPB	Unspecified
13	GLB	Unspecified
14	SHB	Unspecified
15	GHB	Unspecified
16	GHC	Unspecified
17	SHC	Unspecified
18	GLC	Unspecified
19	SPC	Unspecified
20	SNC	Unspecified
21	SOC	Unspecified
22	SOB	Unspecified
23	SOA	Unspecified
24	VREF	Unspecified
25	AGND	Unspecified
26	nFAULT	Unspecified
27	SDO	Unspecified
28	SDI	Unspecified
29	SCLK	Unspecified
30	nSCS	Unspecified
31	ENABLE	Unspecified
32	INHA	Unspecified
33	INLA	Unspecified
34	INHB	Unspecified
35	INLB	Unspecified
36	INHC	Unspecified
37	INLC	Unspecified
38	DVDD	Unspecified
39	GND	Unspecified
40	VGLS	Unspecified
41	EP	Unspecified

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Open-source boards using it

6 layers69.7 × 76.7 mm
Amulet controller
EPFLXplore/XRE_LeggedRobot_HW
PCB designs for Xplore Research's robot dog project
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DRV835FSV2
kavin-x/Quadruped
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78 parts1
6 layers69.7 × 76.7 mm
Amulet controller
aidanbrzezinski/Prism-test
ΛMULET is a high-power brushless motor controller, compatible with the moteus firmware. It was specifically designed to be integrated in EPFL Xplore's Legged Robot actuators.
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Moteus mod n1
Jayanth-M0625/MRL
Work at MRL
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Wheelbase
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Files for SemuBot PCB design.
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Parts like it

Questions

Is there a KiCad symbol and footprint for the DRV8353FSRTAR?

Yes. The symbol is EasyEDA_Cloud:DRV8353FSRTAR and the footprint EasyEDA_Cloud:WQFN-40_L6.0-W6.0-P0.50-TL-EP4.5, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the DRV8353FSRTAR?

WQFN-40-EP(6x6), with 41 pins. Its footprint is drawn on this page.

Where is the DRV8353FSRTAR datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the DRV8353FSRTAR?

JLCPCB lists it as part C1518717, with 668 in stock; the sellers' links on this page open their listings.

What can replace the DRV8353FSRTAR?

Parts like it in the library: the DRV8323SRTAR by Texas Instruments, the DRV8323SRTAT by Texas Instruments and the DRV8353FHRTAR by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the DRV8353FSRTAR?

5 boards in 5 repositories on GitHub; the most starred are listed on this page, with their KiCad files.