Systemverilog

17 boards

KiCad boards from 8 GitHub repositories tagged “systemverilog”, the most starred first; open any of them in PCBKit.

2 layers33 × 71.1 mm
Fpga composite video
Slamy/fpga-composite-video
Verilog implementation of PAL, NTSC and SECAM color encoding
22 parts76MIT
2 layers127 × 76.2 mm
Hx8k brk mem
msinger/iceboy
Game Boy clone for Lattice iCE40 FPGAs
23 parts26
10 layers160 × 100 mm
Cirradio devboard
mangobanaani/cirradio
Tactical UHF FHSS mesh radio: Zynq-7045 + AD9361, SystemVerilog RTL, C++20 comms stack, AES-256 PKCS#11 crypto
316 parts8MIT
4 layers110 × 100 mm
Fidget
transistorfet/fidget
An FPGA board that can interface to the Computie expansion bus using an iCE40HX1K
99 parts4GPL-3.0
4 layers183.4 × 143.1 mm
Motherboard
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
126 parts1
2 layers122 × 81 mm
8-bit cpu
Robert-Riordan-UCD/8_Bit_CPU_FPGA
An 8-bit CPU running on a TangNano 9k FPGA. Written in SystemVerilog and tested with PYUVM.
20 parts1
4 layers80 × 78 mm
Pi5 m2 reference
searchyourmind/fpga-highspeed-daq
SystemVerilog DAQ simulation portfolio: 63 tests, 33 E2E scenarios, DDR3 behavioral and PCIe transaction-level models. Separate PCB design study with retained FAILs; no hardware or timing-closure claims.
34 parts1
2 layers31 × 31 mm
Comparator
vishvish2/BERT_FPGA
Bit Error Rate Tester Project
7 partsMIT
2 layers42.7 × 83.8 mm
Hdmi brd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
42 parts1
2 layers
Hdmi tx
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
20 parts1
2 layers38.1 × 83.8 mm
Iobrd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
22 parts1
2 layers68.6 × 99.1 mm
Lcd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
3 parts1
2 layers30.5 × 83.8 mm
Lcdbrd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
13 parts1
2 layers47 × 83.8 mm
Qm k7 aux brd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
27 parts1
4 layers45.7 × 83.8 mm
Srambrd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
24 parts1
2 layers27.4 × 63.2 mm
Stm32f breakout
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
3 parts1
2 layers129 × 41.9 mm
Usb host hub
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
61 parts1