FPGA SOC

17 boards

KiCad boards from 3 GitHub repositories tagged “fpga-soc”, the most starred first; open any of them in PCBKit.

8 layers167.2 × 100 mm
Marblewalrus switch
azonenberg/antikernel
The Antikernel operating system project
802 parts124
2 layers88 × 88 mm
Acoustic levitation main
leastrobino/acoustic-levitation
Mirror of GitLab repository, all issues and pull requests should be created there.
68 parts21
4 layers183.4 × 143.1 mm
Motherboard
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
126 parts1
4 layers140 × 100 mm
Cat5-tdr
azonenberg/antikernel
The Antikernel operating system project
379 parts124
4 layers203.2 × 128.7 mm
Marblewalrus backplane
azonenberg/antikernel
The Antikernel operating system project
199 parts124
4 layers60 × 100 mm
Usb hub eurocard
azonenberg/antikernel
The Antikernel operating system project
150 parts124
2 layers42 × 37 mm
Uvtest
azonenberg/antikernel
The Antikernel operating system project
16 parts124
2 layers98.8 × 30 mm
Acoustic levitation wing
leastrobino/acoustic-levitation
Mirror of GitLab repository, all issues and pull requests should be created there.
22 parts21
2 layers42.7 × 83.8 mm
Hdmi brd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
42 parts1
2 layers
Hdmi tx
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
20 parts1
2 layers38.1 × 83.8 mm
Iobrd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
22 parts1
2 layers68.6 × 99.1 mm
Lcd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
3 parts1
2 layers30.5 × 83.8 mm
Lcdbrd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
13 parts1
2 layers47 × 83.8 mm
Qm k7 aux brd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
27 parts1
4 layers45.7 × 83.8 mm
Srambrd
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
24 parts1
2 layers27.4 × 63.2 mm
Stm32f breakout
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
3 parts1
2 layers129 × 41.9 mm
Usb host hub
apistol78/rv32
Risc-V pipelined CPU and SoC written in SystemVerilog
61 parts1