4 layers183.4 × 143.1 mmMotherboardapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog126 parts1
2 layers42.7 × 83.8 mmHdmi brdapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog42 parts1
2 layers38.1 × 83.8 mmIobrdapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog22 parts1
2 layers30.5 × 83.8 mmLcdbrdapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog13 parts1
2 layers47 × 83.8 mmQm k7 aux brdapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog27 parts1
4 layers45.7 × 83.8 mmSrambrdapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog24 parts1
2 layers27.4 × 63.2 mmStm32f breakoutapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog3 parts1
2 layers129 × 41.9 mmUsb host hubapistol78/rv32Risc-V pipelined CPU and SoC written in SystemVerilog61 parts1