A7s backplane v2

How the v2 board was made (reproducible pipeline)

This documents exactly how kicad/a7s_backplane_routed.kicad_pcb (the current v2 board) was produced, so it can be reproduced or audited. The one-off scripts for each step are in scripts/.

The intermediate boards these steps produced (a7s_backplane.kicad_pcb build output, _place, _hdrfix, _v2 + its .dsn/.ses) and the _render source board are archived in ../../v1/kicad/ to keep kicad/ to the v2 deliverable. The scripts below use the kicad/ paths as originally run — point them at ../../v1/kicad/ (or regenerate) to reproduce.

Key fact: v2 was not built fresh from build_pcb.py. Its auto-placement is a rough netlist dump (parts off-board, everything overlapping). The usable placement was always hand-done in KiCad. So v2 started from the previous routed board (v1/kicad/a7s_backplane_render.kicad_pcb) and was corrected + re-placed + re-routed. build_pcb.py was only used for the header-orientation fix logic and stays the netlist→initial-placement generator.

Toolchain

The pipeline (in order)

Run each scripts/NN_*.py with tools/kpython unless noted. Filenames are hardcoded in the scripts — read the top of each before running.

0. Netlist (only if connectivity changed). docker run … a7s-skidl python3 a7s_backplane_skidl.py → a7s_backplane.net. The netlist is the connectivity source of truth for every step below.

1. Fix the header mate + make a clean placement canvas — scripts/01_fix_headers_zero_net.py Loads the render board; re-orients J1 → north / J2 → south, centered between their mounting holes, mirrored E-W (the DOA-shorting bug fix); strips all tracks and zeroes all pad nets so you can place freely without a ratsnest. Verifies J1-pin1 aligns E-W with J2-pin15 and that the headers clear the mounting holes.

2. Group logical assemblies — scripts/02a_group_assemblies.py then scripts/02b_group_singles.py Puts each logical unit in a KiCad PCB_GROUP (A7S = J1+J2+H1–H4, RP2040, TFT, BUTTONS, RADIO1/2, JOY, ENC, BTN, each cap/fuse/TP) so a click drags the whole part. Do NOT lock footprints instead — locked footprints become click-through (you select the pad, not the part).

3. Overlay the A7S body + ports as a placement reference — scripts/03_overlay_a7s_ref.py Draws the A7S PCB outline + ETH/USB ports on Dwgs.User, mapped through the 4 mounting holes, and prints the ethernet-edge vs PCB-edge gap. Used to align the A7S 1.75 mm west so the RJ45 edge meets the board edge. (Overlay is removed before fab.)

4. Hand-place in pcbnew. Open the board, drag the groups where they go (arrow keys / M / Ctrl-M "Move Exactly" for precise nudges), save.

5. Re-apply the nets — scripts/04_reapply_nets.py Copies connectivity from the render board back onto the placed board by (ref, pin) — position-independent, so it doesn't matter where parts moved. Writes a7s_backplane_v2.kicad_pcb.

6. Export DSN → route → import SES.

tools/kpython -c "import pcbnew;b=pcbnew.LoadBoard('kicad/a7s_backplane_v2.kicad_pcb');pcbnew.ExportSpecctraDSN(b,'kicad/a7s_backplane_v2.dsn')"
freerouting -de kicad/a7s_backplane_v2.dsn -do kicad/a7s_backplane_v2.ses -mp 15    # MUST be foreground
tools/kpython -c "import pcbnew;b=pcbnew.LoadBoard('kicad/a7s_backplane_v2.kicad_pcb');pcbnew.ImportSpecctraSES(b,'kicad/a7s_backplane_v2.ses');pcbnew.SaveBoard('kicad/a7s_backplane_routed.kicad_pcb',b)"

7. Restore the board outline — scripts/07_restore_edge_cuts.py ImportSpecctraSES silently drops Edge.Cuts segments; this re-adds the south + west edges to close the rectangle. Always re-verify the outline after a route round-trip.

8. Silkscreen labels — scripts/08_silk_labels.py Adds a net/function label tight to every pin (Flipper-header style: ~1.5 mm off the pad, 0.8 mm font), grounds ringed. Back-side parts on B.SilkS (mirrored), TFT on F.SilkS. Single-column connectors label to the interior side; button rows label above.

8b. Credits + easter-egg silkscreen — scripts/08b_silk_credits.py Adds the v2 free-text silk: title/designer block (back, right of the RP2040), special-thanks block (back, left of the RP2040), Flipper-footprint credit (back, behind J12 — the front strip under the J12 pin labels is occupied, the labels are rotated vertical), brand/rev line + HACK THE PLANET (front bottom edge, the visible strip below the buttons), RIP REV 1 memorial (back, between the fuses and J2). All back text is SetMirrored(True). Verified zero new DRC violations vs. the pre-credits baseline.

8c. Logo footprints (silkscreen art) — scripts/08c_logo_footprints.py Traced into a7s.pretty: Amnesia Labs brain (AMNESIA_BRAIN_W20 20×17.4 mm / _W12 12×10.4 mm) and DEF CON 34 jack (DC34_JACK_W30 30 mm / _W20 20 mm — 20 mm is the floor for that art). Full magick/potrace recipes in the script header. pcbnew's Import Graphics crashes on complex SVGs — always use this offline bitmap→potrace→footprint route. fp_poly keeps only ONE outline per shape — emit one PCB_SHAPE per fractured outline or disjoint islands silently vanish on save.

9. Schematic (.kicad_sch) — scripts/09_gen_schematic.py (a copy of tools/gen_kicad_schematic.py) Generates the editable a7s_backplane.kicad_sch from the netlist with kiutils: every component as its stock symbol (RP2040 as a custom box), a global net-label on a wire stub off each pin. Needs the kiutils venv + KICAD_SYM.

10. DRC + fab + renders.

kicad-cli pcb drc --format json --severity-error --severity-warning -o drc.json kicad/a7s_backplane_routed.kicad_pcb
kicad-cli pcb export gerbers -o kicad/fab_v2/ kicad/a7s_backplane_routed.kicad_pcb
kicad-cli pcb export drill --format excellon --excellon-separate-th -o kicad/fab_v2/ kicad/a7s_backplane_routed.kicad_pcb
kicad-cli pcb render --side top    --quality high -o kicad/renders/routed_top.png    kicad/a7s_backplane_routed.kicad_pcb
kicad-cli pcb render --side bottom --quality high -o kicad/renders/routed_bottom.png kicad/a7s_backplane_routed.kicad_pcb

Gotchas (each cost real time)

• freerouting only routes when launched FOREGROUND. nohup/background dies silently. It went 96 → 0 unrouted in ~30 s foreground.
• ImportSpecctraSES silently drops Edge.Cuts — re-run step 7 and check the outline is closed.
• Never lock footprints for hand-placement — locked = click-through (grabs the pad, not the part). Use PCB_GROUPs (step 2).
• pcbnew's process name is the full nix path, so pgrep -x pcbnew false-negatives — match bin/pcbnew. Launch with nohup pcbnew <file> &.
• DRC courtyard "errors" are benign — the TFT (J3) footprint courtyard is the whole floating display, so every part beneath it flags pth_inside_courtyard. Not collisions.
• kiutils quirks (schematic gen): Font(height=,width=) — the 1st positional arg is face; unit sub-symbols must be Part (kiutils appends _unitId_styleId), no lib prefix on units. SKiDL's own generate_schematic() is broken.
• Do not re-run build_pcb.py on a placed/routed board — it emits a rough placed-but-unrouted board and discards the hand-placement + routing.