2 layers80 × 50 mm

Aegis imu carrier
krishharma/aegis-mtstdp
Integer STDP continual-learning core for FPGA (Python golden model + Verilog). Tiny-net co-sim. IMU/power carrier PCB. Tables are simulator results. Not an ASIC.
27 parts
Open-source boards designed in KiCad by krishharma on GitHub, from 1 repository. A board’s address here is its repository’s there.

krishharma/aegis-mtstdp
Integer STDP continual-learning core for FPGA (Python golden model + Verilog). Tiny-net co-sim. IMU/power carrier PCB. Tables are simulator results. Not an ASIC.