Neuromorphic ir event sensor

Neuromorphic Infrared Event Sensor (Rev A)

An analog front-end (AFE) neuromorphic infrared event sensor board designed in KiCad 10. The board implements biologically-inspired temporal contrast sensing across four quadrants (Top-Left, Top-Right, Bottom-Left, Bottom-Right), transducing rapid dynamic changes in infrared illumination into asynchronous digital spike trains suitable for direct FPGA processing.

Full Engineering Design Specification: See docs/DESIGN_SPECIFICATION.md for the frozen 74-section system boundary, optical architecture, TIA/adaptation/comparator parameters, FPGA synchronizer RTL, and verification plans.

3D Isometric View	3D Top View

1. System Overview & Theory of Operation

Architecture Pipeline

Each quadrant operates through an independent analog signal chain:

[Photodiode Pair (BPW34S)]
        │
        ▼
[Transimpedance Amplifier (TIA)]  ──> OPA381 Precision Stage (RF = 18.0k, CF = 47pF, VREF = 1.25V)
        │
        ▼
[High-Pass Differentiator (AC Coupling)] ──> Extracts Temporal Contrast (RA = 22.0k, CA = 100nF, tau = 2.2ms)
        │
        ├──> (+) Positive Threshold Comparator (TLV3202, VTH_ON = 1.29V) ──> ON Event
        └──> (-) Negative Threshold Comparator (TLV3202, VTH_OFF = 1.21V) ──> OFF Event
        │
        ▼
[Monostable Pulse Shaper (74LVC1G123)] ──> Generates Calibrated Digital Spikes (~100 µs)
        │
        ▼
[Digital SPIKE Interface] ──> 2x10 Pin Header (J_FPGA)

Optical Quadrants

• TL (Top-Left): Quadrant 1
• TR (Top-Right): Quadrant 2
• BL (Bottom-Left): Quadrant 3
• BR (Bottom-Right): Quadrant 4
• Center Optical Barrier: Keep-out line ($Y = 27.2\text{ mm}$) separating optical photodiodes from digital pulse-shaping logic with $>1.2\text{ mm}$ clearance.

2. Hardware Specifications

3. Connector Pinouts

J_FPGA: Digital Event Output Header (2x10, 2.54 mm Pitch)

Direct connection to FPGA GPIO bank.

J_DEBUG: Analog Front-End Probe Header (1x6, 2.54 mm Pitch)

Convenient oscilloscope probe points for calibration and signal integrity checking.

4. Circuit Simulation & SPICE Verification

The analog front-end (AFE) and asynchronous spike generation stages have undergone complete SPICE and physical state-space simulation.

Detailed Engineering Report: See docs/SIMULATION_REPORT.md for complete analytical derivations, phase margin calculations, and drift immunity proofs.

Simulation Verification Highlights (Berkeley NGSPICE 46 & Analytical MNA):

• TIA Stability & Phase Margin: 89.1° phase margin at 7.17 MHz crossover frequency ($C_F = 47\text{ pF} \gg C_{F,opt} = 5.86\text{ pF}$). The transimpedance amplifier is strongly overdamped, ensuring zero ringing and unconditional stability.
• Closed-Loop Bandwidth: 190.55 kHz (-3dB cutoff in NGSPICE AC analysis), passing sub-microsecond optical contrast edges while filtering RF noise.
• Temporal Adaptation: High-pass cutoff at 69.18 Hz ($\tau_A = 2.20\text{ ms}$), rejecting steady-state ambient illumination and environmental light drift up to $1.01,\mu\text{A}/\text{ms}$ with zero false spikes.
• Asynchronous Digital Spikes: The 74LVC1G123 monostable generates calibrated $145,\mu\text{s}$ digital CMOS pulses ($0\text{ V} \rightarrow 3.3\text{ V}$) with $< 25\text{ ns}$ comparator propagation delay.

Full AFE Transient Response (NGSPICE 46)	AC Stability & Bode Response (NGSPICE 46)

Microsecond-Scale Spike Timing Detail (NGSPICE 46)

Companion Simulation Files:

• SPICE Netlist: simulation/neuromorphic_afe.cir (native netlist executed via Berkeley NGSPICE 46 / PySpice)
• NGSPICE Runner: simulation/run_spice_simulation.py (python simulation/run_spice_simulation.py)
• Companion Analytical Simulator: simulation/simulate_afe.py (python simulation/simulate_afe.py)

5. Verification Status & DRC Sign-Off

The board has been thoroughly verified using KiCad 10 CLI verification:

• Electrical Connections: 62 nets, 268 pins mapped, 874 track segments, 83 vias.
• Unconnected Nets: 0 (100% routed).
• Short Circuits: 0.
• Clearance Violations: 0.
• Silkscreen Violations: 0 (0 pad overlaps, 0 clipping warnings).
• Physical Placement: 100/100 PASS (0 courtyard collisions, connectors inset $\ge 2.0\text{ mm}$ from board edge, mounting hole clearances $\ge 2.5\text{ mm}$).

6. Turnkey Production Package

Ready-to-manufacture files are located in the production/ and gerbers/ directories:

• 3D CAD STEP Model (Full Assembly): production/neuromorphic-ir-event-sensor-revA.step (Ready for direct import into Onshape, SolidWorks, or FreeCAD for mechanical enclosure/lens housing modeling)
• Gerbers & Drill Archive: production/neuromorphic-ir-event-sensor-revA-gerber.zip
• Bill of Materials: production/neuromorphic-ir-event-sensor-bom.csv (92 components, 27 unique groups)
• Pick-and-Place (CPL): production/neuromorphic-ir-event-sensor-cpl.csv

7. How to Build & Verify (CLI Commands)

Run PCB Design Rule Check (DRC)

kicad-cli pcb drc --format json -o reports/drc_report.json neuromorphic-ir-event-sensor.kicad_pcb

Export Gerbers and Drill Files

kicad-cli pcb export gerbers -o gerbers/ neuromorphic-ir-event-sensor.kicad_pcb
kicad-cli pcb export drill -o gerbers/ neuromorphic-ir-event-sensor.kicad_pcb

Run Berkeley NGSPICE 46 Circuit Simulation

python simulation/run_spice_simulation.py

Run Python Discrete State-Space Simulator

python simulation/simulate_afe.py