2 layers35.6 × 50.6 mm
Proj 3
Rbara00/Rob-Bara-College-Coding-Portfolio
Robert Bara's Electrical Engineering College portfolio
17 parts2
2 layers40.2 × 57.5 mm
Robert Bara's Electrical Engineering College portfolio
- Size
- 40.2 × 57.5 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 29
- Nets
- 34
- Pads
- 116
- Tracks, vias
- 294, 11
- Pours
- 2
- Routed
- Yes
- KiCad
- KiCad 6 (file 20211014)
- Created
- 13 Jan 2021
- Updated
- 18 Dec 2022
Overview
Proj 7 is an open-source printed circuit board by Rbara00, from the Rbara00/Rob-Bara-College-Coding-Portfolio repository on GitHub. It is a 2-layer board of 40.2 × 57.5 mm with 29 parts on 34 nets, routed with 294 tracks and 11 vias.
It is built around the ATMEGA168-20PU, CAT24C512WI-GT3 and DS1337S+T&R. Its parts include 5 resistors, 5 connectors, 4 ICs, 3 capacitors and 3 diodes. It belongs with the AVR (ATmega, ATtiny) boards of this library.
Main components
3
ATMEGA168-20PU
PDIP-28-40℃~+85℃ 10bit 16KB 1KB 2.7V~5.5V 20MHz 23 512Byte 8 Bit AVR Built-in FLASH PDIP-28 Microcontrollers (MCU/MPU/SOC) ROHSMicrochip TechnologyMicrocontrollers (MCU/MPU/SOC)
CAT24C512WI-GT3
SOIC-8-40℃~+85℃ 1,000,000 cycles 1.8V~5.5V 100 Years 1MHz 512Kbit 5ms I2C SOIC-8 EEPROM ROHSonsemiEEPROMDS1337S+T&R
SOIC-8-40℃~+85℃ 1.8V~5.5V 100nA 150uA External I2C Programmable clock output、Alarm function Yes SOIC-8 Real Time Clocks ROHSMaxim Integrated (Analog Devices)Real Time Clocks
README
README.mdRob-Bara-College-Portfolio
A work in Progress College Portfolio of Rob L. Bara. This portfolio demonstrates a variety of lab reports I have created over the course of my college degree, most of which are unedited from the time of submission, so you can understand the mistakes I made as a student, and witness the growth from my mistakes I demonstrate through later labs. Currently consisting of:
-Introduction to C programming Labs
-Introduction to Java Labs
-Digital Circuit Design Lab reports (Verilog)
-Processors Systems Lab reports (Assembly and C)
-Embedded Systems Design Lab reports using Vivado and SDK (C, FreeRTOS, Vivado/Verilog)
-A MATLAB Hangman final project from Engineering Analysis
-Two Analogue Electric Circuits Final Projects with the help of MATLAB and Multisim
-Micro Electronics I Analogue lab reports and final project report using MATLAB and Multisim
-PCB Design consisting of various through hole and surface mount board design using KiCad
-Signals and Systems:Continuous & Discrete-Computer Assignments written in MATLAB
-Stochastic Processes in Signals and Systems Projects as well as a PDF to CDF converter I made
-Digital Communications Lab reports (MATLAB)
-Advanced Processors: Two MIPs Assembly projects and a 32Bit MIPs Single Cycle Processor written in VerilogHDL using Vivado 2019.1
-Engineering Computation II Labs and Projects (Data Structures in C++ and Python)
-Data and Computer Communication Homework and Final Project Report (Networking/Intro to Cloud Computing using Amazon Web Services (AWS) )
-Introduction to Power Electronics Homework and Final Simulink Project (Focuses on DC-DC Buck/Boost Converters)
-For Technical Communication/Writing skills, my Final paper for Technical Communications is avaliable for viewing, which discusses creating a fast-stable real time object detection system for Drones/UAVs. Additionally, the first set of documentation for my Senior Design Project includes a group report discussing the background for a modified Plantar test for Felines to test developments in Spinal Cord Injury models.
-Please request to view my work within Dr Bai's research lab, as it was a government project
-Python Code, CAD files, and documentation for My Senior Design Project can be found here:https://github.com/Rbara00/ThermalLaserSD
Additionally, if you would like a sound portfolio utilizing ProTools or Cubase, please contact me at robert.bara@temple.edu for further discussion
Parts
29| Qty | Value | Footprint | References |
|---|---|---|---|
| 4 | MountingHole | MountingHole:MountingHole_2.5mm | H1, H2, H3, H4 |
| 3 | 10uF | Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder | C1, C2, C3 |
| 3 | 330 | Resistor_SMD:R_2010_5025Metric_Pad1.40x2.65mm_HandSolder | R2, R3, R4 |
| 3 | LED | LED_SMD:LED_0805_2012Metric_Pad1.15x1.40mm_HandSolder | D1, D2, D3 |
| 2 | 10k | Resistor_SMD:R_2010_5025Metric_Pad1.40x2.65mm_HandSolder | R1, R5 |
| 2 | CAT24C512WI-GT3 | Package_SO:SOIC-8_3.9x4.9mm_P1.27mm | U3, U4 |
| 1 | 16kHz | Crystal:Crystal_HC49-4H_Vertical | Y2 |
| 1 | 32kHz | Crystal:Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm_HandSoldering | Y1 |
| 1 | ATmega168-20P | Package_DIP:DIP-28_W7.62mm | U1 |
| 1 | Battery | Connector_PinSocket_2.54mm:PinSocket_1x02_P2.54mm_Vertical | BT1 |
| 1 | Conn_01x02 | Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical | J5 |
| 1 | Conn_01x04 | Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical | J6 |
| 1 | Conn_01x06_Male | Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical | J1 |
| 1 | Conn_01x09_Male | Connector_PinHeader_2.54mm:PinHeader_1x09_P2.54mm_Vertical | J3 |
| 1 | Conn_02x03_Odd_Even | Connector_PinHeader_2.54mm:PinHeader_2x03_P2.54mm_Vertical | J2 |
| 1 | DS1337S+ | IC_Maxim_DS1337S+:Maxim-DS1337S+-Level_A | U2 |
| 1 | LOGO | LOGO | G*** |
| 1 | SW_SPDT | Button_Switch_THT:SW_Slide_1P2T_CK_OS102011MS2Q | SW1 |
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Questions
How big is the Proj 7 PCB?
It measures 40.2 × 57.5 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Proj 7 use?
29 parts, built around the ATMEGA168-20PU, CAT24C512WI-GT3 and DS1337S+T&R. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Proj 7 KiCad files?
From the Rbara00/Rob-Bara-College-Coding-Portfolio repository on GitHub, at the commit this page was made from: the board is ECE4110_PCB_Design/proj_7_Data_Logger/proj_7.kicad_pcb and its schematic ECE4110_PCB_Design/Proj_0IntroToKiCad/Proj_0.kicad_sch. PCBKit opens the board in the browser, with nothing to install.
Can I use the Proj 7 design in my own project?
Its repository states no licence, so its author keeps all rights: ask Rbara00 before reusing the design.