STM32 hardware design Course

Custom STM32F103 Development Board

Overview

This repository contains the KiCad design files and documentation for a custom STM32 development board. Designed from the ground up, this project serves as a highly optimized, component-level alternative to the standard "Blue Pill" modules. The design focuses on robust power delivery, proper analog filtering, and reliable external clock generation, making it an excellent hardware foundation for embedded projects.

This board was designed and routed in KiCad 6, implementing the mixed-signal hardware design methodologies demonstrated by Phil's Lab.

Schematic:

PCB:

Final 3D view:

Hardware Specifications

• Microcontroller: STMicroelectronics STM32F103C8T6 (ARM Cortex-M3)
• Operating Voltage: 3.3V internal logic
• Power Input: 5V via USB Micro-B
• Clocking: 16 MHz High-Speed External (HSE) crystal oscillator with tuned 10pF load capacitors
• Programming/Debugging: 4-pin Serial Wire Debug (SWD) header (3.3V, SWDIO, SWCLK, GND)

Key Features & Component-Level Architecture

• Discrete Power Regulation: Utilizes an AMS1117-3.3 linear voltage regulator for clean 5V to 3.3V step-down, stabilized with 22µF bypass capacitors on the input and output.
• Analog Supply Filtering (VDDA): Implements a dedicated pi-filter network (a 120Ω @ 100MHz ferrite bead paired with 1µF and 10nF capacitors) to isolate the analog supply from digital noise, ensuring accurate ADC conversions.
• Boot Mode Selection: Features an onboard SPDT slide switch tied to the BOOT0 pin (via a 10kΩ series resistor) to easily toggle between standard flash execution and the internal bootloader mode for serial flashing.
• USB 2.0 Full-Speed: Differential USB routing (D+/D-) directly from the micro-B connector, including the required hardware 1.5kΩ pull-up resistor on the D+ line for proper host enumeration.
• Peripheral Breakouts: Dedicated header breakouts for UART and I²C (including onboard pull-up resistors for the SDA and SCL lines).

PCB Design Details

• EDA Tool: KiCad 6
• Layer Stackup: 2-Layer FR4 (1.6mm thickness)
• Top Layer: Signal traces (0.3mm default) and power delivery traces (0.5mm default). Components are grouped logically to keep critical decoupling loops as short as possible.
• Bottom Layer: Solid, uninterrupted ground plane to provide low-impedance return paths and minimize ground loops.
• Vias: Standard 0.7mm pad / 0.3mm drill, utilizing localized "power puddles" (copper pours) to tie decoupled grounds into the bottom plane efficiently.

Repository Contents

• /Hardware: KiCad 6 project files (.kicad_pro, .kicad_sch, .kicad_pcb).
• /Fabrication: Generated Gerber files, NC Drill files, and BOM/CPL (Component Placement List) files formatted for standard PCBA services.
• /3D_Models: STEP files for external connectors to verify mechanical clearances.

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How to Use This Repo

1. View the Schematic: Open the .kicad_sch file to view the component-level connections.
2. Fabrication: Zip the contents of the /Fabrication folder and upload them directly to your preferred PCB manufacturer.
3. Firmware: The board is fully compatible with STM32CubeIDE. Simply select the STM32F103C8T6 target, enable the HSE clock and SWD pins, and begin writing bare-metal C code.