PCM9211PTR

Q: Is there a KiCad symbol and footprint for the PCM9211PTR?

Yes. The symbol is EasyEDA_Cloud:PCM9211PTR and the footprint Package_QFP:TQFP-48_7x7mm_P0.5mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the PCM9211PTR?

TQFP-48(7x7), with 48 pins. Its footprint is drawn on this page.

Q: Where is the PCM9211PTR datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Q: Where can I order the PCM9211PTR?

JLCPCB lists it as part C181660, with 1,337 in stock; the sellers' links on this page open their listings.

Q: What can replace the PCM9211PTR?

Parts like it in the library: the CM108B by Cmedia, the ADAU1701JSTZ-RL by Analog Devices, the HS-100B by Cmedia and the VS1000D-L by VLSI Solution. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the PCM9211PTR?

2 boards in 1 repository on GitHub; the most starred are listed on this page, with their KiCad files.

Texas Instruments

-40℃~+85℃ 2.9V~3.6V、4.5V~5.5V 7kHz~216kHz I2C、SPI Transceiver TQFP-48(7x7) Audio Interface ICs ROHS

Extended

Datasheetti/PCM9211PTR

Category: Audio Interface ICs
Package: TQFP-48(7x7)
Pins: 48

Overview

The PCM9211PTR is an audio Interface IC made by Texas Instruments in a TQFP-48(7x7) package with 48 pins. -40℃~+85℃ 2.9V~3.6V、4.5V~5.5V 7kHz~216kHz I2C、SPI Transceiver TQFP-48(7x7) Audio Interface ICs ROHS.

PCBKit's library has its KiCad symbol (EasyEDA_Cloud:PCM9211PTR, from EasyEDA) and its footprint (Package_QFP:TQFP-48_7x7mm_P0.5mm, from KiCad's library), ready for a KiCad board. 1,337 are in stock at JLCPCB (part C181660). 2 open-source boards in 1 repository on GitHub use it.

Symbol

EasyEDA_Cloud:PCM9211PTRFrom EasyEDA

Footprint

Package_QFP:TQFP-48_7x7mm_P0.5mmFrom KiCad's library

From the datasheet

Supply, least: 2.9 V · VCC, recommended operating min · p. 6
Supply, most: 3.6 V · VCC, recommended operating max · p. 6
Supply, least: 4.5 V · VCCAD, recommended operating min · p. 6
Supply, most: 5.5 V · VCCAD, recommended operating max · p. 6
Supply, absolute maximum: 4 V · VCC, VDD, VDDRX, absolute max · p. 5
Supply, absolute maximum: 6.5 V · VCCAD, absolute max · p. 5
Works from: -40 °C · operating free-air temperature min · p. 6
Works up to: 85 °C · operating free-air temperature max · p. 6
Junction, hottest: 150 °C · operating junction temperature max · p. 5
Takes at most: 48.2 mA · sum of ICC, IDD, ICCAD, IDDRX typical; DIR/DIT at 192 kHz, ADC at 96 kHz · p. 7
Takes asleep: 410 µA · sum of ICC, IDD, ICCAD, IDDRX typical; full power down, RST low · p. 7
Junction to air (PT (LQFP)): 64.5 K/W · junction-to-ambient thermal resistance · p. 6
Junction to case (PT (LQFP)): 19.6 K/W · junction-to-case top thermal resistance · p. 6
Junction to board (PT (LQFP)): 60.1 K/W · junction-to-board thermal resistance · p. 6
Edge: 5 ns · DIR decoded audio outputs, nominal rising time · p. 10

What it is and has

Integration: DIX, ADC, and signal routing · p. 1
Asynchronous operation: DIR, DIT, ADC · p. 1
Audio formats: I2S, left-justified, right-justified · p. 1
DIR: 24-bit, 216-kHz capable · p. 1
DIR jitter: 50 ps · p. 1
Non-PCM detection: IEC61937, DTS-CD/LD · p. 1
S/PDIF input ports: 12 · p. 1
Coaxial S/PDIF inputs: 2 · p. 1
Optical S/PDIF inputs: 10 · p. 1
DIT: 24-bit, 216-kHz capable · p. 1
DIT channel status buffer: 48-bit · p. 1
DIT operation: Synchronous and asynchronous · p. 1
ADC: 24-bit, 96-kHz capable · p. 1
ADC dynamic range: 101 dB at 96 kHz · p. 1
ADC operation: Synchronous, asynchronous · p. 1
Routing inputs: 3x PCM, 1x DIR, 1x ADC · p. 1
Routing outputs: main out, aux out, DIT · p. 1
Multichannel PCM routing: 8 channels · p. 1
Power down: Pin and register control · p. 1
PCM port sampling frequency counter: Available · p. 1
GPIO and GPO: Available · p. 1
External crystal oscillator: 24.576 MHz · p. 1
Control interfaces: SPI, I2C, or hardware control modes · p. 1
Package: 48-pin LQFP · p. 1
PCM ports: Up to 3 IN and up to 3 OUT · p. 16
S/PDIF ports: Up to 12 IN and up to 2 OUT · p. 16

Specifications

177

Parameter	Conditions	As printed	Page
Supply voltage	VCC, VDD, VDDRX	min -0.3 · max 4 V	5
Supply voltage	VCCAD	min -0.3 · max 6.5 V	5
Supply voltage differences: VCC, VDD		max 0.1 V	5
Ground voltage differences: AGND, DGND, GNDRX		max 0.1 V	5
Digital input voltage	RXIN2, RXIN3, RXIN4/ASCKI0, RXIN5/ABCKI0, RXIN6/ALRCKI0, RXIN7/ADIN0, MC/SCL, MDI/SDA, MDO/ADR, MS/ADR1, RST	min -0.3 · max 6.5 V	5
Digital input voltage	MPIO_A0-A3, MPIO_B0-B3, MPIO_C0-C3	min -0.3 · max 6.5 V	5
Digital input voltage	RXIN0, RXIN1 (For S/PDIF TTL / OPTICAL input)	min -0.3 · max 6.5 V	5
Digital input voltage	MODE	min -0.3 · max 4 V	5
Analog input voltage	RXIN0, RXIN1 (For S/PDIF Coaxial Input Only)	min -0.3 V	5
Analog input voltage	XTI, XTO	min -0.3 V	5
Analog input voltage	FILT	min -0.3 V	5
Analog input voltage	VINL, VINR, VCOM	min -0.3 V	5
Input current (any pins except supplies)		max 10 mA	5
Ambient temperature under bias		min -40 · max 125 °C	5
Package temperature (reflow, peak)		max 260 °C	5
Operating Junction temperature TJ		max 150 °C	5
Storage temperature range Tstg		min -55 · max 150 °C	5
Electrostatic discharge V(ESD)	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	max 3000 V	5
Electrostatic discharge V(ESD)	Charged-device model (CDM), per JEDEC specification JESD22-C101	max 750 V	5
DIR analog supply voltage, VCC		min 2.9 · typ 3.3 · max 3.6 V	6
ALL digital supply voltage, VDD		min 2.9 · typ 3.3 · max 3.6 V	6
ADC analog supply voltage, VCCAD		min 4.5 · typ 5 · max 5.5 V	6
Coaxial amplifier supply voltage, VDDRX		min 2.9 · typ 3.3 · max 3.6 V	6
Digital input/output clock frequency	DIR, DIT, and Routing sampling frequency	min 7 · max 216 kHz	6
Digital input/output clock frequency	DIR, DIT, and Routing system clock frequency	min 0.896 · max 55.296 MHz	6
Digital input/output clock frequency	ADC sampling frequency	min 16 · max 96 kHz	6
Digital input/output clock frequency	ADC system clock frequency	min 2.048 · max 24.576 MHz	6
Digital input/output clock frequency	XTI input clock frequency	typ 24.576 MHz	6
Analog input level	VINL, VINR	typ 3 VPP	6
Digital output load capacitance	Except SCKO	max 20 pF	6
Digital output load capacitance	SCKO	max 10 pF	6
MODE pin capacitance		max 10 pF	6
Operating free-air temperature		min -40 · typ 25 · max 85 °C	6
Junction-to-ambient thermal resistance RθJA	PCM9211, PT (LQFP), 48 PINS	typ 64.5 °C/W	6
Junction-to-case (top) thermal resistance RθJC(top)	PCM9211, PT (LQFP), 48 PINS	typ 19.6 °C/W	6
Junction-to-board thermal resistance RθJB	PCM9211, PT (LQFP), 48 PINS	typ 60.1 °C/W	6
Junction-to-top characterization parameter ψJT	PCM9211, PT (LQFP), 48 PINS	typ 0.8 °C/W	6
Junction-to-board characterization parameter ψJB	PCM9211, PT (LQFP), 48 PINS	typ 29.7 °C/W	6
Sampling frequency fS	DIR	min 7 · max 216 kHz	6
Sampling frequency fS	DIT	min 7 · max 216 kHz	6
Sampling frequency fS	Routing	min 7 · max 216 kHz	6
Sampling frequency fS	ADC	min 16 · max 96 kHz	6
Input logic level, high VIH	MPIO_A0-A3, MPIO_B0-B3, MPIOC0-C3, RXIN2-RXIN7, MC/SCL, MDI/SDA, MDO/ADR0, MS/ADR1, RST	min 2 · max 5.5 VDC	6
Input logic level, low VIL	MPIO_A0-A3, MPIO_B0-B3, MPIOC0-C3, RXIN2-RXIN7, MC/SCL, MDI/SDA, MDO/ADR0, MS/ADR1, RST	max 0.8 VDC	6
Input logic current, high IIH	VIN = VDD or VCC; pins in footnotes (2), (4)	max 10 uA	7
Input logic current, low IIL	VIN = 0 V; pins in footnotes (2), (4)	max 10 uA	7
Input logic current, high ( RST pin) IIH	VIN = VDD	typ 65 · max 100 uA	7
Input logic current, low ( RST pin) IIL	VIN = 0 V	max 10 uA	7
Input logic current, high (RXIN0/1 pins) IIH	VIN = VDDRX	typ 165 · max 300 uA	7
Input logic current, low (RXIN0/1 pins) IIL	VIN = 0 V	typ -165 · max -300 uA	7
Output logic level, high VOH	IOUT = –4 mA; MPIO_A0-A3, MPIO_B0-B3, MPIO_C0-C3, SCKO, BCK, LRCK, DOUT, MPO0-1, ERROR/INT0, NPCM/INT1	min 2.8 VDC	7
Output logic level, low VOL	IOUT = 4 mA; MPIO_A0-A3, MPIO_B0-B3, MPIO_C0-C3, SCKO, BCK, LRCK, DOUT, MPO0-1, ERROR/INT0, NPCM/INT1	max 0.5 VDC	7
Voltage range VCC		min 2.9 · typ 3.3 · max 3.6 VDC	7
Voltage range VDD		min 2.9 · typ 3.3 · max 3.6 VDC	7
Voltage range VCCAD		min 4.5 · typ 5 · max 5.5 VDC	7
Voltage range VDDRX		min 2.9 · typ 3.3 · max 3.6 VDC	7
Supply current ICC	fS = 48 kHz / DIR, fS = 48 kHz / ADC, fS = 48 kHz / DIT	typ 4.5 mA	7
Supply current ICC	fS = 192 kHz / DIR, fS = 96 kHz / ADC, fS = 192 kHz / DIT	typ 7 · max 13 mA	7
Supply current ICC	Full power down, RST = low	typ 150 · max 350 uA	7
Supply current IDD	fS = 48 kHz / DIR, fS = 48 kHz / ADC, fS = 48 kHz / DIT	typ 12 mA	7
Supply current IDD	fS = 192 kHz / DIR, fS = 96 kHz / ADC, fS = 192 kHz / DIT	typ 26 · max 38 mA	7
Supply current ICCAD	fS = 192 kHz / DIR, fS = 96 kHz / ADC, fS = 192 kHz / DIT	typ 12 mA	7
Supply current ICCAD	Full power down, RST = low	typ 110 · max 250 uA	7
Supply current IDDRX	fS = 48 kHz / DIR, fS = 48 kHz / ADC, fS = 48 kHz / DIT; two coaxial amplifiers powered on	typ 3.2 mA	7
Supply current IDDRX	fS = 192 kHz / DIR, fS = 96 kHz / ADC, fS = 192 kHz / DIT; two coaxial amplifiers powered on	typ 3.2 · max 4.8 mA	7
Supply current IDDRX	Full power down, RST = low	typ 0 · max 30 uA	7
Power dissipation	fS = 48 kHz / DIR, fS = 48 kHz / ADC, fS = 48 kHz / DIT	typ 135 mW	7
Power dissipation	fS = 192 kHz / DIR, fS = 96 kHz / ADC, fS = 192 kHz / DIT	typ 180 mW	7
Power dissipation	Full power down, RST = low	typ 0.85 mW	7
Operating temperature		min -40 · max 85 °C	7
Thermal resistance RθJA		typ 100 °C/W	7
Resolution		min 16 · typ 24 Bits	8
Sampling frequency fS		min 16 · max 96 kHz	8
Bit clock frequency	64fS	min 1.024 · max 6.144 MHz	8
System clock frequency	256fS	min 4.096 · max 24.576 MHz	8
System clock frequency	512fS	min 8.192 · max 24.576 MHz	8
Input Impedance		typ 10 kΩ	8
Antialiasing filter response	–3 dB	typ 300 kHz	8
Gain mismatch, channel to channel	Full-scale input, VINL, VINR	typ 2 · max 8 % of FSR	8
Gain error	Full-scale input, VINL, VINR	typ 2 · max 8 % of FSR	8
Bipolar zero error	HPF bypass, VINL, VINR	typ 0.5 · max 2 % of FSR	8
THD+N VIN = –1 dB	fS = 48 kHz	typ -93 · max -85 dB	8
THD+N VIN = –1 dB	fS = 96 kHz	typ -93 dB	8
Dynamic range	fS = 48 kHz, A-weighted	min 95 · typ 99 dB	8
Dynamic range	fS = 96 kHz, A-weighted	typ 101 dB	8
S/N ratio	fS = 48 kHz, A-weighted	min 95 · typ 99 dB	8
S/N ratio	fS = 96 kHz, A-weighted	typ 101 dB	8
Channel separation (between L-ch and R-ch)	fS = 48 kHz	min 92 · typ 96 dB	8
Channel separation (between L-ch and R-ch)	fS = 96 kHz	typ 98 dB	8
Passband ripple	< 0.454 fS	max 0.05 dB	8
Stop band attenuation	> 0.583 fS	min -65 dB	8
VCOM output impedance		min 7 · typ 12.5 · max 18 kΩ	8
Allowable VCOM output source/sink current		max 1 uA	8
Input resistance	DIR, coaxial input amplifier (RXIN0 and RXIN1)	typ 20 kΩ	9
Input voltage	DIR, coaxial input amplifier (RXIN0 and RXIN1)	min 0.15 VPP	9
Input hysteresis	DIR, coaxial input amplifier (RXIN0 and RXIN1)	typ 50 mV	9
Input sampling frequency	DIR, coaxial input amplifier (RXIN0 and RXIN1)	min 7 · max 216 kHz	9
Input biphase sampling frequency range	Normal mode	min 28 · max 108 kHz	9
Input biphase sampling frequency range	Wide mode	min 7 · max 216 kHz	9
PLL lock up time	From biphase signal detection to error out release (ERROR = L); ERRWT = 11	max 100 ms	9
Serial audio data width	DIR, recovered clock and data	min 16 · max 24 Bits	9
System clock frequency	DIR, recovered clock and data; 128fS	min 0.896 · max 27.648 MHz	9
System clock frequency	DIR, recovered clock and data; 256fS	min 1.792 · max 55.296 MHz	9
System clock frequency	DIR, recovered clock and data; 512fS	min 3.584 · max 55.296 MHz	9
Bit clock frequency	DIR, recovered clock and data; 64fS	min 0.448 · max 13.824 MHz	9
LR clock frequency	DIR, recovered clock and data; fS	min 7 · max 216 kHz	9
System clock jitter	fS = 48 kHz, SCKO = 256fS, measured period jitter	typ 50 · max 100 ps, rms	9
Output biphase sampling frequency	DIT	min 7 · max 216 kHz	9
Input system clock frequency	DIT; 128fS	min 0.896 · max 27.648 MHz	9
Input system clock frequency	DIT; 256fS	min 1.792 · max 55.296 MHz	9
Input system clock frequency	DIT; 512fS	min 3.584 · max 55.296 MHz	9
Input bit clock frequency	DIT; 64fS	min 0.448 · max 13.824 MHz	9
Input LR clock frequency	DIT; fS	min 7 · max 216 kHz	9
XTI source clock frequency		typ 24.576 MHz	9
Frequency accuracy	Oscillator circuit, XTI and XMCKO clock	min -100 · max 100 ppm	9
XMCKO frequency		typ 24.576 MHz	9
System clock frequency	PCM output port (SCKO, BCK, LRCK, DOUT); 128fS / 256fS / 512fS	min 0.896 · max 55.296 MHz	9
Bit clock output frequency	PCM output port (SCKO, BCK, LRCK, DOUT); 64fS	min 0.448 · max 13.824 MHz	9
LR clock output frequency	PCM output port (SCKO, BCK, LRCK, DOUT); fS	min 7 · max 216 kHz	9
System clock frequency	Routing; 128fS / 256fS / 512fS	min 0.896 · max 55.296 MHz	9
Bit clock output Frequency	Routing; 64fS	min 0.448 · max 13.824 MHz	9
LR clock output frequency	Routing; fS	min 7 · max 216 kHz	9
RST pulse width ( RST pin = low) tRSTL	RST pin device reset requirements	min 1 us	10
System clock cycle time tSCY	ADC system clock input; ADCLK = AUXIN0, AUXIN1 or AUXIN2	min 30 ns	10
BCK cycle time tBCY	Audio data interface, slave mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 75 ns	10
BCK high time tBCH	Audio data interface, slave mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 35 ns	10
BCK low time tBCL	Audio data interface, slave mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 35 ns	10
LRCK setup time to BCK rising edge tLRS	Audio data interface, slave mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 10 ns	10
LRCK hold time to BCK rising edge tLRH	Audio data interface, slave mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 10 ns	10
DOUT delay time from BCK falling edge tDOD	Audio data interface, slave mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 10 · max 70 ns	10
LRCK delay time to BCK falling edge tLRD	Audio data interface, master mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 0 · max 30 ns	10
DOUT delay time from BCK falling edge tDOD	Audio data interface, master mode; output load 20 pF; ADCLK = AUXIN0, AUXIN1 or AUXIN2; SCK < 25 MHz	min 0 · max 30 ns	10
System clock pulse cycle time tSCY	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	min 18 ns	10
Delay time of BCKO falling edge to LRCKO valid tCKLR	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	min -10 · max 10 ns	10
BCKO pulse width high tBCH	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	min 60 ns	10
BCKO pulse width low tBCL	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	min 60 ns	10
Delay time of BCKO falling edge to DOUT valid tBCDO	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	min -10 · max 10 ns	10
Rising time of all signals tR	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	typ 5 ns	10
Falling time of all signals tF	DIR decoded audio data output; LRCKO, BCKO, DOUT load 20 pF	typ 5 ns	10
MC Pulse cycle time tMCY	Control interface requirements, four wire SCI	min 100 ns	10
MC Low level time tMCL	Control interface requirements, four wire SCI	min 40 ns	10
MC High level time tMCH	Control interface requirements, four wire SCI	min 40 ns	10
MS Falling edge to MC rising edge tMSS	Control interface requirements, four wire SCI	min 30 ns	10
MS Rising edge from MC rising edge for LSB tMSH	Control interface requirements, four wire SCI	min 15 ns	10
MDI Hold time tMDH	Control interface requirements, four wire SCI	min 15 ns	10
MDI Set-up time tMDS	Control interface requirements, four wire SCI	min 15 ns	10
MDO Enable or delay time from MC falling edge tMDD	Control interface requirements, four wire SCI	min 0 · max 30 ns	10
MDO Disable time from MS rising edge tMDR	Control interface requirements, four wire SCI	min 0 · max 30 ns	10
SCL clock frequency fSCL	Control interface, SCL and SDA, standard mode	max 100 kHz	11
Bus free time between STOP and START condition tBUF	Control interface, SCL and SDA, standard mode	min 4.7 us	11
Low period of the SCL clock tLOW	Control interface, SCL and SDA, standard mode	min 4.7 us	11
High period of the SCL clock tHI	Control interface, SCL and SDA, standard mode	min 4 us	11
Setup time for START/Repeated START condition tS-SU	Control interface, SCL and SDA, standard mode	min 4.7 us	11
Hold time for START/Repeated START condition tS-HD	Control interface, SCL and SDA, standard mode	min 4 us	11
Data setup time tD-SU	Control interface, SCL and SDA, standard mode	min 250 ns	11
Data hold time tD-HD	Control interface, SCL and SDA, standard mode	min 0 · max 3450 ns	11
Rise time of SCL signal tSCL-R	Control interface, SCL and SDA, standard mode	max 1000 ns	11
Fall time of SCL signal tSCL-F	Control interface, SCL and SDA, standard mode	max 1000 ns	11
Rise time of SDA signal tSDA-R	Control interface, SCL and SDA, standard mode	max 1000 ns	11
Fall time of SDA signal tSDA-F	Control interface, SCL and SDA, standard mode	max 1000 ns	11
Setup time for STOP condition tP-SU	Control interface, SCL and SDA, standard mode	min 4 us	11
Capacitive load for SDA and SCL line CB	Control interface, SCL and SDA, standard mode	max 400 pF	11
SCL clock frequency fSCL	Control interface, SCL and SDA, fast mode	max 400	11
Bus free time between STOP and START condition tBUF	Control interface, SCL and SDA, fast mode	min 1.3	11
Low period of the SCL clock tLOW	Control interface, SCL and SDA, fast mode	min 1.3	11
High period of the SCL clock tHI	Control interface, SCL and SDA, fast mode	min 0.6	11
Setup time for START/Repeated START condition tS-SU	Control interface, SCL and SDA, fast mode	min 0.6	11
Hold time for START/Repeated START condition tS-HD	Control interface, SCL and SDA, fast mode	min 0.6	11
Data setup time tD-SU	Control interface, SCL and SDA, fast mode	min 100	11
Data hold time tD-HD	Control interface, SCL and SDA, fast mode	min 0 · max 900	11
Rise time of SCL signal tSCL-R	Control interface, SCL and SDA, fast mode	max 300	11
Fall time of SCL signal tSCL-F	Control interface, SCL and SDA, fast mode	max 300	11
Rise time of SDA signal tSDA-R	Control interface, SCL and SDA, fast mode	max 300	11
Fall time of SDA signal tSDA-F	Control interface, SCL and SDA, fast mode	max 300	11
Setup time for STOP condition tP-SU	Control interface, SCL and SDA, fast mode	min 0.6	11
Allowable glitch width tGW	Control interface, SCL and SDA, fast mode	max 50	11
Capacitive load for SDA and SCL line CB	Control interface, SCL and SDA, fast mode	max 100	11

Pins, by the datasheet

1 ERROR/INT0: DIR error detection output / interrupt 0 output. · p. 3
2 NPCM/INT1: DIR non-PCM detection output / interrupt 1 output. · p. 3
3 MPIO_A0: Multipurpose I/O, group A; Schmitt trigger input, 5-V tolerant. · p. 3
4 MPIO_A1: Multipurpose I/O, group A; Schmitt trigger input, 5-V tolerant. · p. 3
5 MPIO_A2: Multipurpose I/O, group A; Schmitt trigger input, 5-V tolerant. · p. 3
6 MPIO_A3: Multipurpose I/O, group A; Schmitt trigger input, 5-V tolerant. · p. 3
7 MPIO_C0: Multipurpose I/O, group C; Schmitt trigger input, 5-V tolerant. · p. 3
8 MPIO_C1: Multipurpose I/O, group C; Schmitt trigger input, 5-V tolerant. · p. 3
9 MPIO_C2: Multipurpose I/O, group C; Schmitt trigger input, 5-V tolerant. · p. 3
10 MPIO_C3: Multipurpose I/O, group C; Schmitt trigger input, 5-V tolerant. · p. 3
11 MPIO_B0: Multipurpose I/O, group B; Schmitt trigger input, 5-V tolerant. · p. 3
12 MPIO_B1: Multipurpose I/O, group B; Schmitt trigger input, 5-V tolerant. · p. 3
13 MPIO_B2: Multipurpose I/O, group B; Schmitt trigger input, 5-V tolerant. · p. 3
14 MPIO_B3: Multipurpose I/O, group B; Schmitt trigger input, 5-V tolerant. · p. 4
15 MPO0: Multipurpose output 0. · p. 4
16 MPO1: Multipurpose output 1. · p. 4
17 DOUT: Main output port, serial digital audio data output. · p. 4
18 LRCK: Main output port, LR clock output. · p. 4
19 BCK: Main output port, bit clock output. · p. 4
20 SCKO: Main output port, system clock output. · p. 4
21 DGND: Ground for digital. · p. 4
22 DVDD: Digital power supply, 3.3 V typical. · p. 4
23 MDO/ADR0: SPI data output / I2C slave address setting 0; Schmitt trigger input, 5-V tolerant. · p. 4
24 MDI/SDA: SPI data input / I2C data input/output; open-drain in I2C mode, Schmitt trigger input, 5-V tolerant. · p. 4
25 MC/SCL: SPI clock input / I2C clock input; Schmitt trigger input, 5-V tolerant. · p. 4
26 MS/ADR1: SPI chip select / I2C slave address setting 1; Schmitt trigger input, 5-V tolerant. · p. 4
27 MODE: Control mode setting. · p. 4
28 RXIN7/ADIN0: Biphase signal input 7 / AUXIN0 serial audio data input; Schmitt trigger input, 5-V tolerant. · p. 4
29 RXIN6/ALRCKI0: Biphase signal input 6 / AUXIN0 LR clock input; Schmitt trigger input, 5-V tolerant. · p. 4
30 RXIN5/ABCKI0: Biphase signal input 5 / AUXIN0 bit clock input; Schmitt trigger input, 5-V tolerant. · p. 4
31 RXIN4/ASCKI0: Biphase signal input 4 / AUXIN0 system clock input; Schmitt trigger input, 5-V tolerant. · p. 4
32 RXIN3: Biphase signal input 3; Schmitt trigger input, 5-V tolerant. · p. 4
33 RXIN2: Biphase signal input 2; Schmitt trigger input, 5-V tolerant. · p. 4
34 RST: Active-low reset input with Schmitt trigger and onboard 50 kΩ typical pulldown; 5-V tolerant. · p. 4
35 RXIN1: Biphase signal input 1 with built-in coaxial amplifier; 5-V tolerant. · p. 4
36 VDDRX: Power supply for RXIN0 and RXIN1, 3.3 V typical. · p. 4
37 RXIN0: Biphase signal input 0 with built-in coaxial amplifier; 5-V tolerant. · p. 4
38 GNDRX: Ground for RXIN. · p. 4
39 XTI: Oscillation circuit input for crystal resonator or external XTI clock source; CMOS Schmitt trigger input. · p. 4
40 XTO: Oscillation circuit output for crystal resonator. · p. 4
41 AGND: Ground for PLL analog. · p. 4
42 VCC: Power supply for PLL analog, 3.3 V typical. · p. 4
43 FILT: External PLL loop filter connection terminal; must connect recommended filter. · p. 4
44 VCOM: ADC common voltage output; must connect external decoupling capacitor. · p. 4
45 AGNDAD: Ground for ADC analog. · p. 4
46 VCCAD: Power supply for ADC analog, 5.0 V typical. · p. 4
47 VINL: ADC analog voltage input, left channel. · p. 4
48 VINR: ADC analog voltage input, right channel. · p. 4

Parameters

Current - Supply(Max): 48.2mA
Features: Multi-channel audio
Interface: SPI
Junction Temperature(Max): 150℃
Operating Temperature: -40℃~+85℃
Rise Time: 5ns
Sampling Rate: 7kHz~216kHz
Standby Current: 410uA
Thermal Resistance(Junction to Ambient): 64.5℃/W
Thermal Resistance(Junction to Board): 60.1℃/W
Thermal Resistance(Junction to Case): 19.6℃/W
Type: Transceiver
Voltage - Supply: 2.9V~5.5V
Voltage - Supply(Absolute Max): 4V

Order codes

PCM9211PTRLCSC C181660

Pinout

The pins of the PCM9211PTR
Pin	Name	Type
1	ERROR/INT0	Output
2	NPCM/INT1	Output
3	MPIO_A0	Input/output
4	MPIO_A1	Input/output
5	MPIO_A2	Input/output
6	MPIO_A3	Input/output
7	MPIO_C0	Input/output
8	MPIO_C1	Input/output
9	MPIO_C2	Input/output
10	MPIO_C3	Input/output
11	MPIO_B0	Input/output
12	MPIO_B1	Input/output
13	MPIO_B2	Input/output
14	MPIO_B3	Input/output
15	MPO0	Output
16	MPO1	Output
17	DOUT	Output
18	LRCK	Output
19	BCK	Output
20	SCKO	Output
21	DGND	Unspecified
22	DVDD	Unspecified
23	MDO/ADR0	Input/output
24	MDI/SDA	Input/output
25	MC/SCL	Unspecified
26	MS/ADR1	Unspecified
27	MODE	Unspecified
28	RXIN7/ADIN0	Unspecified
29	RXIN6/ALRCKI0	Unspecified
30	RXIN5/ABCKI0	Unspecified
31	RXIN4/ASCKI0	Unspecified
32	RXIN3	Unspecified
33	RXIN2	Unspecified
34	RST#	Unspecified
35	RXIN1	Unspecified
36	VDDRX	Unspecified
37	RXIN0	Unspecified
38	GNDRX	Unspecified
39	XTI	Unspecified
40	XTO	Unspecified
41	AGND	Unspecified
42	VCC	Unspecified
43	FILT	Unspecified
44	VCOM	Output
45	AGNDAD	Unspecified
46	VCCAD	Unspecified
47	VINL	Unspecified
48	VINR	Unspecified

Open-source boards using it

All 2

4 layers100 × 90 mm
Endstufe
LeanderGlanda/Endstufe
Custom designed 2.1 active crossover amplifier board
198 parts2
4 layers85 × 50 mm
InputBoard
LeanderGlanda/Endstufe
Custom designed 2.1 active crossover amplifier board
65 parts2

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Questions

Is there a KiCad symbol and footprint for the PCM9211PTR?

Yes. The symbol is EasyEDA_Cloud:PCM9211PTR and the footprint Package_QFP:TQFP-48_7x7mm_P0.5mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the PCM9211PTR?

TQFP-48(7x7), with 48 pins. Its footprint is drawn on this page.

Where is the PCM9211PTR datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the PCM9211PTR?

JLCPCB lists it as part C181660, with 1,337 in stock; the sellers' links on this page open their listings.

What can replace the PCM9211PTR?

Parts like it in the library: the CM108B by Cmedia, the ADAU1701JSTZ-RL by Analog Devices, the HS-100B by Cmedia and the VS1000D-L by VLSI Solution. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the PCM9211PTR?

2 boards in 1 repository on GitHub; the most starred are listed on this page, with their KiCad files.

PCM9211PTR

Overview

Symbol

Footprint

From the datasheet

What it is and has

Specifications

Pins, by the datasheet

Parameters

Order codes

Pinout

Open-source boards using it

Endstufe

InputBoard

Show this part on your page

Questions

Is there a KiCad symbol and footprint for the PCM9211PTR?

What package is the PCM9211PTR?

Where is the PCM9211PTR datasheet?

Where can I order the PCM9211PTR?

What can replace the PCM9211PTR?

Which open-source boards use the PCM9211PTR?

Parts like it

CM108B

ADAU1701JSTZ-RL

HS-100B

VS1000D-L

VS1003B-L

ADAU1701JSTZ

VS1053B-L

ISD3900FYI