STM32F070CBT6

Q: Is there a KiCad symbol and footprint for the STM32F070CBT6?

Yes. The symbol is MCU_ST_STM32F0:STM32F070CBTx and the footprint Package_QFP:LQFP-48_7x7mm_P0.5mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the STM32F070CBT6?

LQFP-48(7x7), with 48 pins. Its footprint is drawn on this page.

Q: Where is the STM32F070CBT6 datasheet?

STMicroelectronics publishes it: the Datasheet link on this page opens it.

Q: Where can I order the STM32F070CBT6?

JLCPCB lists it as part C74909, with 1,579 in stock; the sellers' links on this page open their listings.

Q: What can replace the STM32F070CBT6?

Parts like it in the library: the STM32F103C8T6 by STMicroelectronics, the STM32F030C8T6 by STMicroelectronics, the STM32G070CBT6 by STMicroelectronics and the STM32G030C8T6 by STMicroelectronics. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the STM32F070CBT6?

11 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

STMicroelectronicsExtended

-40℃~+85℃ 128KB 12bit 16KB 2.4V~3.6V 32 Bit 37 48MHz ARM Cortex-M0 Built-in FLASH LQFP-48(7x7) Microcontrollers (MCU/MPU/SOC) ROHS

Datasheet JLCPCB LCSC

Part id: st/STM32F070CBT6
Category: Microcontrollers (MCU, MPU, SOC)
Package: LQFP-48(7x7)
Pins: 48
In stock: 1,579 at JLCPCB (C74909)
Used on: 11 open-source boards

Overview

The STM32F070CBT6 is a microcontroller made by STMicroelectronics in a LQFP-48(7x7) package with 48 pins. -40℃~+85℃ 128KB 12bit 16KB 2.4V~3.6V 32 Bit 37 48MHz ARM Cortex-M0 Built-in FLASH LQFP-48(7x7) Microcontrollers (MCU/MPU/SOC) ROHS.

PCBKit's library has its KiCad symbol (MCU_ST_STM32F0:STM32F070CBTx, from KiCad's library) and its footprint (Package_QFP:LQFP-48_7x7mm_P0.5mm, from KiCad's library), ready for a KiCad board. 1,579 are in stock at JLCPCB (part C74909). 11 open-source boards in 4 repositories on GitHub use it.

Symbol

MCU_ST_STM32F0:STM32F070CBTxFrom KiCad's library

Footprint

Package_QFP:LQFP-48_7x7mm_P0.5mmFrom KiCad's library

From the datasheet

Supply, least: 2.4 V · VDD, recommended operating min · p. 39
Supply, most: 3.6 V · VDD, recommended operating max · p. 39
Supply, absolute maximum: 4 V · VDD, absolute max · p. 38
Works from: -40 °C · Ambient min, suffix 6 · p. 40
Works up to: 85 °C · Ambient max, suffix 6, maximum power dissipation · p. 40
Works up to: 105 °C · Ambient max, suffix 6, low power dissipation; junction must remain within limit · p. 40
Junction, hottest: 105 °C · Junction recommended operating max, suffix 6 · p. 40
Junction, hottest: 150 °C · Junction absolute max · p. 39
Takes asleep: 6.5 µA · sum of VDD and VDDA typical Stop currents, regulator low-power, oscillators off, VDDA monitoring on, 3.6 V · p. 43
A pin gives at most: 25 mA · I/O sink absolute max per pin · p. 39
Junction to air (LQFP48 - 7 mm x 7 mm): 55 K/W · Junction-to-ambient thermal resistance · p. 79
Supply, least: 3 V · VDD, USB transceiver operating min · p. 69
A pin gives at most: 20 mA · GPIO source or sink max with relaxed VOL/VOH · p. 58

What it is and has

Core: ARM 32-bit Cortex-M0 · p. 1
Maximum CPU frequency: 48 MHz · p. 10
Flash memory: 128 Kbytes · p. 10
SRAM: 16 Kbytes · p. 10
GPIOs: 37 · p. 10
SPI: 2 · p. 10
I2C: 2 · p. 10
USART: 4 · p. 10
USB: 1 · p. 10
ADC: 12-bit, 1 converter · p. 10
ADC channels: 10 external + 2 internal · p. 10
DMA: 5 channels · p. 1
CRC: Calculation unit · p. 1
Low-power modes: Sleep, Stop, Standby · p. 1
Reset: Power-on/Power down reset · p. 1
Debug: Serial wire debug · p. 1
Package: LQFP48 · p. 10
Core: ARM 32-bit Cortex-M0 CPU · p. 1
Core clock: Up to 48 MHz · p. 1
CRC: CRC calculation unit · p. 1
Reset: Power-on/Power down reset (POR/PDR) · p. 1
Core: ARM® 32-bit Cortex®-M0 CPU · p. 1
Flash memory: 128 Kbyte · p. 80
CRC calculation unit: Present · p. 1
ADC resolution: 12-bit · p. 61
USB: USB 2.0 Full-speed device; USB-IF certified · p. 69

Around it

cap 5 pF to 20 pF: between OSC_IN and GND; CL1, typical range; high-quality external ceramic capacitor for high-frequency applications. Select for crystal load requirements and place close to oscillator pins. · p. 48

Specifications

264

Parameter	Conditions	As printed	Page
External main supply voltage VDD–VSS		min -0.3 · max 4 V	38
External analog supply voltage VDDA–VSS		min -0.3 · max 4 V	38
Allowed voltage difference for VDD > VDDA VDD–VDDA	VDD > VDDA	max 0.4 V	38
Input voltage on TTa pins VIN	Min VSS −0.3	max 4 V	38
BOOT0 VIN	Max VDDIOx + 4.0	min 0 V	38
Input voltage on any other pin VIN	Min VSS − 0.3	max 4 V	38
Variations between different VDD power pins \|ΔVDDx\|		max 50 mV	38
Variations between all the different ground pins \|VSSx − VSS\|		max 50 mV	38
Total current into sum of all VDD power lines (source) ΣIVDD		max 120 mA	39
Total current out of sum of all VSS ground lines (sink) ΣIVSS		max -120 mA	39
Maximum current into each VDD power pin (source) IVDD(PIN)		max 100 mA	39
Maximum current out of each VSS ground pin (sink) IVSS(PIN)		max -100 mA	39
Output current sunk by any I/O and control pin IIO(PIN)		max 25 mA	39
Output current source by any I/O and control pin IIO(PIN)		max -25 mA	39
Total output current sunk by sum of all I/Os and control pins ΣIIO(PIN)		max 80 mA	39
Total output current sourced by sum of all I/Os and control pins ΣIIO(PIN)		max -80 mA	39
Storage temperature range TSTG		min -65 · max 150 °C	39
Maximum junction temperature TJ	Absolute maximum	max 150 °C	39
Internal AHB clock frequency fHCLK		min 0 · max 48 MHz	39
Internal APB clock frequency fPCLK		min 0 · max 48 MHz	39
Standard operating voltage VDD		min 2.4 · max 3.6 V	39
Analog operating voltage VDDA	Must have a potential equal to or higher than VDD	min 2.4 · max 3.6 V	40
I/O input voltage VIN	TC and RST I/O; max VDDIOx+0.3	min -0.3 V	40
I/O input voltage VIN	TTa I/O; max VDDA+0.3	min -0.3 V	40
I/O input voltage VIN	FT and FTf I/O	min -0.3 · max 5.5 V	40
I/O input voltage VIN	BOOT0	min 0 · max 5.5 V	40
Power dissipation at TA = 85 °C for suffix 6 PD	STM32F070CB, LQFP48	max 364 mW	40
Ambient temperature for the suffix 6 version TA	Maximum power dissipation	min -40 · max 85 °C	40
Ambient temperature for the suffix 6 version TA	Low power dissipation; TJ must not exceed TJmax	min -40 · max 105 °C	40
Junction temperature range TJ	Suffix 6 version	min -40 · max 105 °C	40
VDD rise time rate tVDD	Max ∞	min 0 us/V	40
VDD fall time rate tVDD	Max ∞	min 20 us/V	40
VDDA rise time rate tVDDA	Max ∞	min 0 us/V	40
VDDA fall time rate tVDDA	Max ∞	min 20 us/V	40
Power on/power down reset threshold VPOR/PDR	Falling edge	min 1.8 · typ 1.88 · max 1.96 V	40
Power on/power down reset threshold VPOR/PDR	Rising edge	min 1.84 · typ 1.92 · max 2 V	40
Supply current in Run mode, code executing from Flash IDD	48 MHz; HSI or HSE clock, PLL on; all peripherals enabled; max at TA = 85 °C	typ 24.1 · max 27.6 mA	42
Supply current in Run mode, code executing from Flash IDD	24 MHz; HSI or HSE clock, PLL on; all peripherals enabled; max at TA = 85 °C	typ 12.4 · max 14.4 mA	42
Supply current in Run mode, code executing from Flash IDD	8 MHz; HSI or HSE clock, PLL off; all peripherals enabled; max at TA = 85 °C	typ 4.52 · max 5.28 mA	42
Supply current in Run mode, code executing from RAM IDD	48 MHz; HSI or HSE clock, PLL on; all peripherals enabled; max at TA = 85 °C	typ 23.1 · max 25 mA	42
Supply current in Run mode, code executing from RAM IDD	24 MHz; HSI or HSE clock, PLL on; all peripherals enabled; max at TA = 85 °C	typ 11.5 · max 13.6 mA	42
Supply current in Run mode, code executing from RAM IDD	8 MHz; HSI or HSE clock, PLL off; all peripherals enabled; max at TA = 85 °C	typ 4.34 · max 5.03 mA	42
Supply current in Sleep mode, code executing from Flash or RAM IDD	48 MHz; HSI or HSE clock, PLL on; all peripherals enabled; max at TA = 85 °C	typ 15 · max 17.3 mA	42
Supply current in Sleep mode, code executing from Flash or RAM IDD	24 MHz; HSI or HSE clock, PLL on; all peripherals enabled; max at TA = 85 °C	typ 7.53 · max 8.87 mA	42
Supply current in Sleep mode, code executing from Flash or RAM IDD	8 MHz; HSI or HSE clock, PLL off; all peripherals enabled; max at TA = 85 °C	typ 2.95 · max 3.41 mA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL on; 48 MHz; max at TA = 85 °C	typ 165 · max 196 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; 8 MHz; max at TA = 85 °C	typ 3.6 · max 5.2 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; 1 MHz; max at TA = 85 °C	typ 3.6 · max 5.2 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL on; 48 MHz; max at TA = 85 °C	typ 245 · max 279 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL off; 8 MHz; max at TA = 85 °C	typ 83.4 · max 95.3 uA	42
Supply current in Stop mode IDD	VDD = VDDA = 3.6 V; regulator in run mode, all oscillators OFF; max at TA = 85 °C	typ 15.9 · max 49 uA	43
Supply current in Stop mode IDD	VDD = VDDA = 3.6 V; regulator in low-power mode, all oscillators OFF; max at TA = 85 °C	typ 3.7 · max 33 uA	43
Supply current in Standby mode IDD	VDD = VDDA = 3.6 V; LSI ON and IWDG ON	typ 1.5 uA	43
Supply current in Stop mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring ON; regulator in run or low-power mode, all oscillators OFF; max at TA = 85 °C	typ 2.8 · max 3.6 uA	43
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring ON; LSI ON and IWDG ON	typ 3.5 uA	43
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring ON; LSI OFF and IWDG OFF; max at TA = 85 °C	typ 2.6 · max 3.6 uA	43
Supply current in Stop mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring OFF; regulator in run or low-power mode, all oscillators OFF	typ 1.5 uA	43
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring OFF; LSI ON and IWDG ON	typ 2.2 uA	43
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring OFF; LSI OFF and IWDG OFF	typ 1.4 uA	43
Electrostatic discharge voltage (human body model) VESD(HBM)	TA = +25 °C, conforming to JESD22-A114; all packages; class 2	max 2000 V	54
Electrostatic discharge voltage (charge device model) VESD(CDM)	TA = +25 °C, conforming to ANSI/ESD STM5.3.1; all packages; class C4	max 500 V	54
Schmitt trigger hysteresis Vhys	TC and TTa I/O	typ 200 mV	55
Schmitt trigger hysteresis Vhys	FT and FTf I/O	typ 100 mV	55
Schmitt trigger hysteresis Vhys	BOOT0	typ 300 mV	55
Input leakage current Ilkg	TTa in digital mode; VDDIOx ≤ VIN ≤ VDDA	max 1 uA	56
Input leakage current Ilkg	FT and FTf I/O; VDDIOx ≤ VIN ≤ 5 V	max 10 uA	56
Weak pull-up equivalent resistor RPU	VIN = VSS	min 25 · typ 40 · max 55 kΩ	56
Weak pull-down equivalent resistor RPD	VIN = VDDIOx	min 25 · typ 40 · max 55 kΩ	56
I/O pin capacitance CIO		typ 5 pF	56
Output low level voltage for an I/O pin VOL	\|IIO\| = 8 mA; VDDIOx ≥ 2.7 V	max 0.4 V	58
Output low level voltage for an I/O pin VOL	\|IIO\| = 20 mA; VDDIOx ≥ 2.7 V	max 1.3 V	58
Output low level voltage for an I/O pin VOL	\|IIO\| = 6 mA	max 0.4 V	58
Output low level voltage for an FTf I/O pin in Fm+ mode VOLFm+	\|IIO\| = 20 mA; VDDIOx ≥ 2.7 V	max 0.4 V	58
Output low level voltage for an FTf I/O pin in Fm+ mode VOLFm+	\|IIO\| = 10 mA	max 0.4 V	58
Maximum frequency fmax(IO)out	OSPEEDRy = x0; CL = 50 pF, VDDIOx ≥ 2.4 V	max 2 MHz	59
Output fall time tf(IO)out	OSPEEDRy = x0; CL = 50 pF, VDDIOx ≥ 2.4 V	max 125 ns	59
Output rise time tr(IO)out	OSPEEDRy = x0; CL = 50 pF, VDDIOx ≥ 2.4 V	max 125 ns	59
Maximum frequency fmax(IO)out	OSPEEDRy = 01; CL = 50 pF, VDDIOx ≥ 2.4 V	max 10 MHz	59
Output fall time tf(IO)out	OSPEEDRy = 01; CL = 50 pF, VDDIOx ≥ 2.4 V	max 25 ns	59
Output rise time tr(IO)out	OSPEEDRy = 01; CL = 50 pF, VDDIOx ≥ 2.4 V	max 25 ns	59
Maximum frequency fmax(IO)out	OSPEEDRy = 11; CL = 30 pF, VDDIOx ≥ 2.7 V	max 50 MHz	59
Maximum frequency fmax(IO)out	OSPEEDRy = 11; CL = 50 pF, VDDIOx ≥ 2.7 V	max 30 MHz	59
Maximum frequency fmax(IO)out	OSPEEDRy = 11; CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V	max 20 MHz	59
Output fall time tf(IO)out	OSPEEDRy = 11; CL = 30 pF, VDDIOx ≥ 2.7 V	max 5 ns	59
Output fall time tf(IO)out	OSPEEDRy = 11; CL = 50 pF, VDDIOx ≥ 2.7 V	max 8 ns	59
Output fall time tf(IO)out	OSPEEDRy = 11; CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V	max 12 ns	59
Output rise time tr(IO)out	OSPEEDRy = 11; CL = 30 pF, VDDIOx ≥ 2.7 V	max 5 ns	59
Output rise time tr(IO)out	OSPEEDRy = 11; CL = 50 pF, VDDIOx ≥ 2.7 V	max 8 ns	59
Output rise time tr(IO)out	OSPEEDRy = 11; CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V	max 12 ns	59
Maximum frequency fmax(IO)out	Fm+ configuration; CL = 50 pF, VDDIOx ≥ 2.4 V	max 2 MHz	59
Output fall time tf(IO)out	Fm+ configuration; CL = 50 pF, VDDIOx ≥ 2.4 V	max 12 ns	59
Output rise time tr(IO)out	Fm+ configuration; CL = 50 pF, VDDIOx ≥ 2.4 V	max 34 ns	59
Pulse width of external signals detected by the EXTI controller tEXTIpw		min 10 ns	59
Thermal resistance junction-ambient ΘJ	LQFP48 - 7 mm x 7 mm	typ 55 °C/W	79
BOOT0 VIN	Max VDDIOx + 4.0 V; VDDIOx internally connected to VDD	min 0 V	38
Injected current on TC and RST pin IINJ(PIN)	Maximum magnitude ±5 mA	max 5 mA	39
Injected current on TTa pins IINJ(PIN)	Maximum magnitude ±5 mA	max 5 mA	39
Total injected current (sum of all I/O and control pins) ΣIINJ(PIN)	Absolute sum of positive and negative injected currents; maximum magnitude ±25 mA	max 25 mA	39
Maximum junction temperature TJ		max 150 °C	39
I/O input voltage VIN	TC and RST I/O; max VDDIOx+0.3 V	min -0.3 V	40
I/O input voltage VIN	TTa I/O; max VDDA+0.3 V	min -0.3 V	40
Power dissipation at TA = 85 °C for suffix 6 PD	LQFP48	max 364 mW	40
PDR hysteresis VPDRhyst		typ 40 mV	41
Reset temporization tRSTTEMPO		min 1.5 · typ 2.5 · max 4.5 ms	41
Internal reference voltage VREFINT	-40°C < TA < +85°C	min 1.2 · typ 1.23 · max 1.25 V	41
ADC_IN17 buffer startup time tSTART		max 10 us	41
ADC sampling time when reading the internal reference voltage tS_vrefint		min 4 us	41
Internal reference voltage spread over the temperature range ΔVREFINT	VDDA = 3 V	max 10 mV	41
Temperature coefficient TCoeff		min -100 · max 100 ppm/°C	41
Supply current in Run mode, code executing from Flash IDD	All peripherals enabled; HSI or HSE clock, PLL on; fHCLK = 48 MHz; max at TA = 85 °C	typ 24.1 · max 27.6 mA	42
Supply current in Run mode, code executing from Flash IDD	All peripherals enabled; HSI or HSE clock, PLL on; fHCLK = 24 MHz; max at TA = 85 °C	typ 12.4 · max 14.4 mA	42
Supply current in Run mode, code executing from Flash IDD	All peripherals enabled; HSI or HSE clock, PLL off; fHCLK = 8 MHz; max at TA = 85 °C	typ 4.52 · max 5.28 mA	42
Supply current in Run mode, code executing from RAM IDD	All peripherals enabled; HSI or HSE clock, PLL on; fHCLK = 48 MHz; max at TA = 85 °C	typ 23.1 · max 25 mA	42
Supply current in Run mode, code executing from RAM IDD	All peripherals enabled; HSI or HSE clock, PLL on; fHCLK = 24 MHz; max at TA = 85 °C	typ 11.5 · max 13.6 mA	42
Supply current in Run mode, code executing from RAM IDD	All peripherals enabled; HSI or HSE clock, PLL off; fHCLK = 8 MHz; max at TA = 85 °C	typ 4.34 · max 5.03 mA	42
Supply current in Sleep mode, code executing from Flash or RAM IDD	All peripherals enabled; HSI or HSE clock, PLL on; fHCLK = 48 MHz; max at TA = 85 °C	typ 15 · max 17.3 mA	42
Supply current in Sleep mode, code executing from Flash or RAM IDD	All peripherals enabled; HSI or HSE clock, PLL on; fHCLK = 24 MHz; max at TA = 85 °C	typ 7.53 · max 8.87 mA	42
Supply current in Sleep mode, code executing from Flash or RAM IDD	All peripherals enabled; HSI or HSE clock, PLL off; fHCLK = 8 MHz; max at TA = 85 °C	typ 2.95 · max 3.41 mA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL on; fHCLK = 48 MHz; max at TA = 85 °C	typ 165 · max 196 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; fHCLK = 8 MHz; max at TA = 85 °C	typ 3.6 · max 5.2 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; fHCLK = 1 MHz; max at TA = 85 °C	typ 3.6 · max 5.2 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL on; fHCLK = 48 MHz; max at TA = 85 °C	typ 245 · max 279 uA	42
Supply current in Run or Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL off; fHCLK = 8 MHz; max at TA = 85 °C	typ 83.4 · max 95.3 uA	42
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals enabled	typ 23.5 mA	44
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals disabled	typ 13.5 mA	44
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals enabled	typ 4.8 mA	44
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals disabled	typ 3.1 mA	44
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals enabled	typ 163.3 uA	44
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals disabled	typ 163.3 uA	44
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals enabled	typ 2.5 uA	44
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals disabled	typ 2.5 uA	44
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 0 pF; C = CINT + CEXT+ CS; fSW = 4 MHz	typ 0.18 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 0 pF; C = CINT + CEXT+ CS; fSW = 8 MHz	typ 0.37 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 0 pF; C = CINT + CEXT+ CS; fSW = 16 MHz	typ 0.76 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 0 pF; C = CINT + CEXT+ CS; fSW = 24 MHz	typ 1.39 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 0 pF; C = CINT + CEXT+ CS; fSW = 48 MHz	typ 2.188 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 22 pF; C = CINT + CEXT+ CS; fSW = 4 MHz	typ 0.49 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 22 pF; C = CINT + CEXT+ CS; fSW = 8 MHz	typ 0.94 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 22 pF; C = CINT + CEXT+ CS; fSW = 16 MHz	typ 2.38 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 22 pF; C = CINT + CEXT+ CS; fSW = 24 MHz	typ 3.99 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 47 pF; C = CINT + CEXT+ CS; fSW = 4 MHz	typ 0.81 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 47 pF; C = CINT + CEXT+ CS; fSW = 8 MHz	typ 1.7 mA	45
I/O current consumption ISW	VDDIOx = 3.3 V; CEXT = 47 pF; fSW = 16 MHz	typ 3.67 mA	45
Wakeup from Stop mode tWUSTOP	Regulator in run mode; VDD = VDDA = 3.3 V	typ 2.8 · max 5 us	46
Wakeup from Standby mode tWUSTANDBY	VDD = VDDA = 3.3 V	typ 51 us	46
User external clock source frequency fHSE_ext		typ 8 · max 32 MHz	46
OSC_IN high or low time tw(HSEH), tw(HSEL)		min 15 ns	46
OSC_IN rise or fall time tr(HSE), tf(HSE)		max 20 ns	46
User external clock source frequency fLSE_ext		typ 32.768 · max 1000 kHz	47
OSC32_IN high or low time tw(LSEH), tw(LSEL)		min 450 ns	47
OSC32_IN rise or fall time tr(LSE), tf(LSE)		max 50 ns	47
Oscillator frequency fOSC_IN		min 4 · typ 8 · max 32 MHz	47
Feedback resistor RF		typ 200 kΩ	47
HSE current consumption IDD	During startup; first 2/3 of tSU(HSE)	max 8.5 mA	48
HSE current consumption IDD	VDD = 3.3 V; Rm = 45 Ω; CL = 10 pF@8 MHz	typ 0.5 mA	48
HSE current consumption IDD	VDD = 3.3 V; Rm = 30 Ω; CL = 20 pF@32 MHz	typ 1.5 mA	48
Oscillator transconductance gm	Startup	min 10 mA/V	48
Startup time tSU(HSE)	VDD is stabilized; standard 8 MHz crystal resonator	typ 2 ms	48
LSE current consumption IDD	low drive capability	typ 0.5 · max 0.9 uA	49
LSE current consumption IDD	medium-low drive capability	max 1 uA	49
LSE current consumption IDD	medium-high drive capability	max 1.3 uA	49
LSE current consumption IDD	high drive capability	max 1.6 uA	49
Oscillator transconductance gm	low drive capability	min 5 uA/V	49
Oscillator transconductance gm	medium-low drive capability	min 8 uA/V	49
Oscillator transconductance gm	medium-high drive capability	min 15 uA/V	49
Oscillator transconductance gm	high drive capability	min 25 uA/V	49
Startup time tSU(LSE)	VDDIOx is stabilized	typ 2 s	49
LSI oscillator startup time tsu(LSI)	VDDA = 3.3 V, TA = -40 to 85 °C	max 85 us	51
LSI oscillator power consumption IDDA(LSI)	VDDA = 3.3 V, TA = -40 to 85 °C	typ 0.75 uA	51
PLL input clock fPLL_IN		min 1 · typ 8 · max 24 MHz	51
PLL input clock duty cycle fPLL_IN		min 40 · max 60 %	51
PLL multiplier output clock fPLL_OUT		min 16 · max 48 MHz	51
PLL lock time tLOCK		max 200 us	51
Cycle-to-cycle jitter JitterPLL		max 300 ps	51
16-bit programming time tprog	TA = -40 to +85 °C	typ 53.5 us	51
Page erase time tERASE	TA = -40 to +85 °C; STM32F070xB page size 2KB	typ 30 ms	51
Mass erase time tME	TA = -40 to +85 °C	typ 30 ms	51
Supply current IDD	Write mode; TA = -40 to 85 °C	max 10 mA	51
Supply current IDD	Erase mode; TA = -40 to 85 °C	max 12 mA	51
Programming voltage Vprog	TA = -40 to 85 °C	min 2.4 · max 3.6 V	51
Electrostatic discharge voltage (human body model) VESD(HBM)	All packages; TA = +25 °C, conforming to JESD22-A114; Class 2	max 2000 V	54
Electrostatic discharge voltage (charge device model) VESD(CDM)	All packages; TA = +25 °C, conforming to ANSI/ESD STM5.3.1; Class C4	max 500 V	54
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = x0; CL = 50 pF, VDDIOx ≥ 2.4 V	max 2 MHz	59
Output fall time tf(IO)out	OSPEEDRy[1:0] = x0; CL = 50 pF, VDDIOx ≥ 2.4 V	max 125 ns	59
Output rise time tr(IO)out	OSPEEDRy[1:0] = x0; CL = 50 pF, VDDIOx ≥ 2.4 V	max 125 ns	59
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 01; CL = 50 pF, VDDIOx ≥ 2.4 V	max 10 MHz	59
Output fall time tf(IO)out	OSPEEDRy[1:0] = 01; CL = 50 pF, VDDIOx ≥ 2.4 V	max 25 ns	59
Output rise time tr(IO)out	OSPEEDRy[1:0] = 01; CL = 50 pF, VDDIOx ≥ 2.4 V	max 25 ns	59
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 11; CL = 30 pF, VDDIOx ≥ 2.7 V	max 50 MHz	59
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDDIOx ≥ 2.7 V	max 30 MHz	59
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V	max 20 MHz	59
Output fall time tf(IO)out	OSPEEDRy[1:0] = 11; CL = 30 pF, VDDIOx ≥ 2.7 V	max 5 ns	59
Output fall time tf(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDDIOx ≥ 2.7 V	max 8 ns	59
Output fall time tf(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V	max 12 ns	59
Output rise time tr(IO)out	OSPEEDRy[1:0] = 11; CL = 30 pF, VDDIOx ≥ 2.7 V	max 5 ns	59
Output rise time tr(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDDIOx ≥ 2.7 V	max 8 ns	59
Output rise time tr(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, 2.4 V ≤VDDIOx < 2.7 V	max 12 ns	59
Analog supply voltage for ADC ON VDDA		min 2.4 · max 3.6 V	61
Current consumption of the ADC IDDA (ADC)	VDD = VDDA = 3.3 V	typ 0.9 mA	61
ADC clock frequency fADC		min 0.6 · max 14 MHz	61
Sampling rate fS		min 0.05 · max 1 MHz	61
External trigger frequency fTRIG	fADC = 14 MHz	max 823 kHz	61
External trigger frequency fTRIG		max 17 1/fADC	61
Conversion voltage range VAIN	Maximum VDDA	min 0 V	61
External input impedance RAIN	See Equation 1 and Table 50 for details	max 50 kΩ	61
Sampling switch resistance RADC		max 1 kΩ	61
Internal sample and hold capacitor CADC		max 8 pF	61
Calibration time tCAL	fADC = 14 MHz	typ 5.9 us	62
Calibration time tCAL		typ 83 1/fADC	62
ADC_DR register write latency WLATENCY	ADC clock = PCLK/2	typ 4.5 fPCLK cycle	62
ADC_DR register write latency WLATENCY	ADC clock = PCLK/4	typ 8.5 fPCLK cycle	62
Trigger conversion latency tlatr	fADC = fPCLK/2 = 14 MHz	typ 0.196 us	62
Trigger conversion latency tlatr	fADC = fPCLK/2	typ 5.5 1/fPCLK	62
Trigger conversion latency tlatr	fADC = fPCLK/4 = 12 MHz	typ 0.219 us	62
Trigger conversion latency tlatr	fADC = fPCLK/4	typ 10.5 1/fPCLK	62
Trigger conversion latency tlatr	fADC = fHSI14 = 14 MHz	min 0.188 · max 0.259 us	62
ADC jitter on trigger conversion JitterADC	fADC = fHSI14	typ 1 1/fHSI14	62
Sampling time tS	fADC = 14 MHz	min 0.107 · max 17.1 us	62
Sampling time tS		min 1.5 · max 239.5 1/fADC	62
Stabilization time tSTAB		typ 14 1/fADC	62
Total conversion time (including sampling time) tCONV	fADC = 14 MHz, 12-bit resolution	min 1 · max 18 us	62
Total conversion time (including sampling time) tCONV	12-bit resolution; tS for sampling +12.5 for successive approximation	min 14 · max 252 1/fADC	62
RAIN max RAIN	Ts = 1.5 cycles; tS = 0.11 us	max 0.4 kΩ	63
RAIN max RAIN	Ts = 7.5 cycles; tS = 0.54 us	max 5.9 kΩ	63
RAIN max RAIN	Ts = 13.5 cycles; tS = 0.96 us	max 11.4 kΩ	63
RAIN max RAIN	Ts = 28.5 cycles; tS = 2.04 us	max 25.2 kΩ	63
RAIN max RAIN	Ts = 41.5 cycles; tS = 2.96 us	max 37.2 kΩ	63
RAIN max RAIN	Ts = 55.5 cycles; tS = 3.96 us	max 50 kΩ	63
Total unadjusted error ET	Symmetric ± error; after internal calibration; fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C	typ 3.3 · max 4 LSB	63
Offset error EO	Symmetric ± error; after internal calibration; fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C	typ 1.9 · max 2.8 LSB	63
Gain error EG	Symmetric ± error; after internal calibration; fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C	typ 2.8 · max 3 LSB	63
Differential linearity error ED	Symmetric ± error; after internal calibration; fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C	typ 0.7 · max 1.3 LSB	63
Integral linearity error EL	Symmetric ± error; after internal calibration; fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C	typ 1.2 · max 1.7 LSB	63
Timeout period	Prescaler divider /4; PR[2:0] = 0; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 0.1 · max 409.6 ms	66
Timeout period	Prescaler divider /8; PR[2:0] = 1; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 0.2 · max 819.2 ms	66
Timeout period	Prescaler divider /16; PR[2:0] = 2; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 0.4 · max 1638.4 ms	66
Timeout period	Prescaler divider /32; PR[2:0] = 3; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 0.8 · max 3276.8 ms	66
Timeout period	Prescaler divider /64; PR[2:0] = 4; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 1.6 · max 6553.6 ms	66
Timeout period	Prescaler divider /128; PR[2:0] = 5; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 3.2 · max 13107.2 ms	66
Timeout period	Prescaler divider /256; PR[2:0] = 6 or 7; minimum RL[11:0] = 0x000, maximum RL[11:0] = 0xFFF	min 6.4 · max 26214.4 ms	66
Timeout value	Prescaler = 1; WDGTB = 0	min 0.0853 · max 5.4613 ms	66
Timeout value	Prescaler = 2; WDGTB = 1	min 0.1706 · max 10.9226 ms	66
Timeout value	Prescaler = 4; WDGTB = 2	min 0.3413 · max 21.8453 ms	66
Timeout value	Prescaler = 8; WDGTB = 3	min 0.6826 · max 43.6906 ms	66
Maximum pulse width of spikes that are suppressed by the analog filter tAF		min 50 · max 260 ns	67
SPI clock frequency fSCK; 1/tc(SCK)	Master mode	max 18 MHz	67
SPI clock frequency fSCK; 1/tc(SCK)	Slave mode	max 18 MHz	67
SPI clock rise and fall time tr(SCK); tf(SCK)	Capacitive load: C = 15 pF	max 6 ns	67
Data input setup time tsu(MI)	Master mode	min 4 ns	67
Data input setup time tsu(SI)	Slave mode	min 5 ns	67
Data input hold time th(MI)	Master mode	min 4 ns	67
Data input hold time th(SI)	Slave mode	min 5 ns	67
Data output access time ta(SO)	Slave mode, fPCLK = 20 MHz; maximum 3Tpclk	min 0 ns	67
Data output disable time tdis(SO)	Slave mode	min 0 · max 18 ns	67
Data output valid time tv(SO)	Slave mode (after enable edge)	max 22.5 ns	67
Data output valid time tv(MO)	Master mode (after enable edge)	max 6 ns	67
Data output hold time th(SO)	Slave mode (after enable edge)	min 11.5 ns	67
Data output hold time th(MO)	Master mode (after enable edge)	min 2 ns	67
SPI slave input clock duty cycle DuCy(SCK)	Slave mode	min 25 · max 75 %	67
USB transceiver operating voltage VDD		min 3 · max 3.6 V	69
USB transceiver startup time tSTARTUP		max 1 us	69
Embedded USB_DP pull-up value during idle RPUI		min 1.1 · typ 1.26 · max 1.5 kΩ	69
Embedded USB_DP pull-up value during reception RPUR		min 2 · typ 2.26 · max 2.6 kΩ	69
Output driver impedance ZDRV	Driving high and low	min 28 · typ 40 · max 44 Ω	69

Pins, by the datasheet

1 VDD: Digital power supply. · p. 26
2 PC13: GPIO; WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT. Output must not source current. · p. 26
7 NRST: Device reset input / internal reset output, active low. · p. 26
8 VSSA: Analog ground. · p. 26
9 VDDA: Analog power supply. · p. 26
10 PA0: GPIO; USART2_CTS, USART4_TX, RTC_TAMP2, WKUP1, ADC_IN0. · p. 26
11 PA1: GPIO; USART2_RTS, TIM15_CH1N, USART4_RX, EVENTOUT, ADC_IN1. · p. 26
12 PA2: GPIO; USART2_TX, TIM15_CH1, ADC_IN2, WKUP4. · p. 26
13 PA3: GPIO; USART2_RX, TIM15_CH2, ADC_IN3. · p. 26
14 PA4: GPIO; SPI1_NSS, TIM14_CH1, USART2_CK, ADC_IN4. · p. 26
15 PA5: GPIO; SPI1_SCK, ADC_IN5. · p. 26
16 PA6: GPIO; SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT, USART3_CTS, ADC_IN6. · p. 27
17 PA7: GPIO; SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT, ADC_IN7. · p. 27
18 PB0: GPIO; TIM3_CH3, TIM1_CH2N, EVENTOUT, USART3_CK, ADC_IN8. · p. 27
19 PB1: GPIO; TIM3_CH4, USART3_RTS, TIM14_CH1, TIM1_CH3N, ADC_IN9. · p. 27
20 PB2: GPIO. · p. 27
21 PB10: GPIO; SPI2_SCK, USART3_TX. · p. 27
22 PB11: GPIO; USART3_RX, EVENTOUT, I2C2_SDA. · p. 27
23 VSS: Ground. · p. 27
24 VDD: Digital power supply. · p. 27
25 PB12: GPIO; TIM1_BKIN, TIM15_BKIN, SPI2_NSS, EVENTOUT, USART3_CK. · p. 27
26 PB13: GPIO; SPI2_SCK, I2C2_SCL, TIM1_CH1N, USART3_CTS. · p. 27
27 PB14: GPIO; SPI2_MISO, I2C2_SDA, TIM1_CH2N, TIM15_CH1, USART3_RTS. · p. 27
28 PB15: GPIO; SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, WKUP7, RTC_REFIN. · p. 27
29 PA8: GPIO; USART1_CK, TIM1_CH1, EVENTOUT, MCO. · p. 28
30 PA9: GPIO; USART1_TX, TIM1_CH2, TIM15_BKIN. · p. 28
31 PA10: GPIO; USART1_RX, TIM1_CH3, TIM17_BKIN. · p. 28
32 PA11: GPIO; USART1_CTS, TIM1_CH4, EVENTOUT, USB_DM. · p. 28
33 PA12: GPIO; USART1_RTS, TIM1_ETR, EVENTOUT, USB_DP. · p. 28
34 PA13: GPIO; IR_OUT, SWDIO, USB_NOE. SWDIO with internal pull-up after reset. · p. 28
35 VSS: Ground. · p. 28
36 VDD: Digital power supply. · p. 28
37 PA14: GPIO; USART2_TX, SWCLK. SWCLK with internal pull-down after reset. · p. 28
38 PA15: GPIO; SPI1_NSS, USART2_RX, USART4_RTS, EVENTOUT. · p. 28
39 PB3: GPIO; SPI1_SCK, EVENTOUT. · p. 28
40 PB4: GPIO; SPI1_MISO, TIM17_BKIN, TIM3_CH1, EVENTOUT. · p. 28
41 PB5: GPIO; SPI1_MOSI, I2C1_SMBA, TIM16_BKIN, TIM3_CH2, WKUP6. · p. 28
42 PB6: GPIO; I2C1_SCL, USART1_TX, TIM16_CH1N. · p. 28
43 PB7: GPIO; I2C1_SDA, USART1_RX, USART4_CTS, TIM17_CH1N. · p. 29
44 BOOT0: Boot memory selection. · p. 29
45 PB8: GPIO; I2C1_SCL, TIM16_CH1. · p. 29
46 PB9: GPIO; SPI2_NSS, I2C1_SDA, IR_OUT, TIM17_CH1, EVENTOUT. · p. 29
47 VSS: Ground. · p. 29
48 VDD: Digital power supply. · p. 29

Parameters

ADC (Bit): 12bit
CPU Core: ARM Cortex-M0
CPU Maximum Speed: 48MHz
Core Size: 32 Bit
Junction Temperature(Max): 105℃
Number of I/O: 37
Operating Temperature: -40℃~+105℃
Oscillator Type: Built-in
Output Current per Pin(Max): 25mA
Program Memory Type: FLASH
Program Storage Size: 128KB
RAM Size: 16KB
Standby Current: 6.5uA
Thermal Resistance(Junction to Ambient): 55℃/W
Voltage - Supply: 2.4V~3.6V
Voltage - Supply(Absolute Max): 4V

Order codes

STM32F070CBT6TRLCSC C2053863
STM32F070CBT6LCSC C74909

Pinout

The pins of the STM32F070CBT6
Pin	Name	Type
1	VDD	Power in
2	PC13	Input/output
3	PC14	Input/output
4	PC15	Input/output
5	PF0	Input/output
6	PF1	Input/output
7	NRST	Input
8	VSSA	Power in
9	VDDA	Power in
10	PA0	Input/output
11	PA1	Input/output
12	PA2	Input/output
13	PA3	Input/output
14	PA4	Input/output
15	PA5	Input/output
16	PA6	Input/output
17	PA7	Input/output
18	PB0	Input/output
19	PB1	Input/output
20	PB2	Input/output
21	PB10	Input/output
22	PB11	Input/output
23	VSS	Power in
24	VDD	Power in
25	PB12	Input/output
26	PB13	Input/output
27	PB14	Input/output
28	PB15	Input/output
29	PA8	Input/output
30	PA9	Input/output
31	PA10	Input/output
32	PA11	Input/output
33	PA12	Input/output
34	PA13	Input/output
35	VSS	Passive
36	VDD	Power in
37	PA14	Input/output
38	PA15	Input/output
39	PB3	Input/output
40	PB4	Input/output
41	PB5	Input/output
42	PB6	Input/output
43	PB7	Input/output
44	BOOT0	Input
45	PB8	Input/output
46	PB9	Input/output
47	VSS	Passive
48	VDD	Power in

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Questions

Is there a KiCad symbol and footprint for the STM32F070CBT6?

Yes. The symbol is MCU_ST_STM32F0:STM32F070CBTx and the footprint Package_QFP:LQFP-48_7x7mm_P0.5mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the STM32F070CBT6?

LQFP-48(7x7), with 48 pins. Its footprint is drawn on this page.

Where is the STM32F070CBT6 datasheet?

STMicroelectronics publishes it: the Datasheet link on this page opens it.

Where can I order the STM32F070CBT6?

JLCPCB lists it as part C74909, with 1,579 in stock; the sellers' links on this page open their listings.

What can replace the STM32F070CBT6?

Parts like it in the library: the STM32F103C8T6 by STMicroelectronics, the STM32F030C8T6 by STMicroelectronics, the STM32G070CBT6 by STMicroelectronics and the STM32G030C8T6 by STMicroelectronics. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the STM32F070CBT6?

11 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

STM32F070CBT6

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Open-source boards using it

Pif fpga

Usb thermo logger

Jaguar USB tap

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