STM32F030F4P6

Q: Is there a KiCad symbol and footprint for the STM32F030F4P6?

Yes. The symbol is MCU_ST_STM32F0:STM32F030F4Px and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the STM32F030F4P6?

TSSOP-20, with 20 pins. Its footprint is drawn on this page.

Q: Where is the STM32F030F4P6 datasheet?

STMicroelectronics publishes it: the Datasheet link on this page opens it.

Q: Where can I order the STM32F030F4P6?

JLCPCB lists it as part C89040, with 59,987 in stock; the sellers' links on this page open their listings.

Q: What can replace the STM32F030F4P6?

Parts like it in the library: the CH32V003F4P6 by WCH (Nanjing Qinheng Microelectronics), the STM32G030F6P6 by STMicroelectronics, the STM32F042F4P6 by STMicroelectronics and the STM32F042F6P6 by STMicroelectronics. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Q: Which open-source boards use the STM32F030F4P6?

41 boards in 30 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

STMicroelectronicsExtended

-40℃~+85℃ 12bit 15 16KB 2.4V~3.6V 32 Bit 48MHz 4KB ARM Cortex-M0 Built-in FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHS

Datasheet JLCPCB LCSC

Part id: st/STM32F030F4P6
Category: Microcontrollers (MCU, MPU, SOC)
Package: TSSOP-20
Pins: 20
In stock: 59,987 at JLCPCB (C89040)
Used on: 41 open-source boards

Overview

The STM32F030F4P6 is a microcontroller made by STMicroelectronics in a TSSOP-20 package with 20 pins. -40℃~+85℃ 12bit 15 16KB 2.4V~3.6V 32 Bit 48MHz 4KB ARM Cortex-M0 Built-in FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHS.

PCBKit's library has its KiCad symbol (MCU_ST_STM32F0:STM32F030F4Px, from KiCad's library) and its footprint (Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, from KiCad's library), ready for a KiCad board. 59,987 are in stock at JLCPCB (part C89040). 41 open-source boards in 30 repositories on GitHub use it.

Symbol

MCU_ST_STM32F0:STM32F030F4PxFrom KiCad's library

Footprint

Package_SO:TSSOP-20_4.4x6.5mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 2.4 V · VDD, recommended operating minimum · p. 40
Supply, most: 3.6 V · VDD, recommended operating maximum · p. 40
Supply, absolute maximum: 4 V · VDD and VDDA, absolute maximum · p. 38
Works from: -40 °C · minimum ambient, suffix 6, maximum power dissipation · p. 40
Works up to: 85 °C · maximum ambient, suffix 6, maximum power dissipation · p. 40
Works up to: 105 °C · maximum ambient at low power dissipation, subject to TJ maximum · p. 40
Junction, hottest: 105 °C · maximum operating junction temperature, suffix 6 · p. 40
Junction, hottest: 150 °C · absolute maximum junction temperature · p. 39
Takes working: 23.46 mA · sum of VDD and VDDA typical run currents, 48 MHz, Flash, peripherals enabled, 3.3 V · p. 45
Takes asleep: 5.3 µA · sum of VDD and VDDA typical standby currents, LSI and IWDG on, VDDA monitoring on, 3.6 V · p. 44
A pin gives at most: 25 mA · absolute maximum current sunk by any I/O and control pin · p. 39
Junction to air (TSSOP20): 110 K/W · junction-to-ambient thermal resistance · p. 83
A pin gives at most: 20 mA · GPIO source or sink max, relaxed VOL/VOH · p. 60

What it is and has

Core: ARM 32-bit Cortex-M0 CPU · p. 1
Maximum CPU frequency: 48 MHz · p. 1
CRC: CRC calculation unit · p. 1
DMA: 5-channel controller · p. 1
Low power modes: Sleep, Stop, Standby · p. 1
Reset: Power-on/Power down reset (POR/PDR) · p. 1
Debug: Serial wire debug (SWD) · p. 1
CPU frequency: up to 48 MHz · p. 1
Basic timer: One 16-bit basic timer · p. 1
Watchdog timers: Independent and system watchdog timers · p. 1
SysTick: 24-bit downcounter · p. 1
Crystal oscillator: 4 to 32 MHz · p. 1
ADC: 12-bit · p. 64

Around it

diode Schottky: between standard analog input pin and ground; Recommended for standard analog pins which may inject negative current. · p. 65

Specifications

233

Parameter	Conditions	As printed	Page
External main supply voltage (including VDDA and VDD) VDD–VSS	Absolute maximum ratings	min -0.3 · max 4 V	38
Allowed voltage difference for VDD > VDDA VDD–VDDA	VDD > VDDA	max 0.4 V	38
Input voltage on TTa pins VIN	Minimum VSS  0.3	max 4 V	38
Input voltage on any other pin VIN	Minimum VSS 0.3	max 4 V	38
Variations between different VDD power pins \|VDDx\|		max 50 mV	38
Variations between all the different ground pins \|VSSX VSS\|		max 50 mV	38
Total current into sum of all VDD_x and VDDSDx power lines (source) IVDD	Absolute maximum ratings	max 120 mA	39
Total current out of sum of all VSS_x and VSSSD ground lines (sink) IVSS	Absolute maximum ratings	max -120 mA	39
Maximum current into each VDD_x or VDDSDx power pin (source) IVDD(PIN)	Absolute maximum ratings	max 100 mA	39
Maximum current out of each VSS_x or VSSSD ground pin (sink) IVSS(PIN)	Absolute maximum ratings	max -100 mA	39
Output current sunk by any I/O and control pin IIO(PIN)	Absolute maximum ratings	max 25 mA	39
Output current source by any I/O and control pin IIO(PIN)	Absolute maximum ratings	max -25 mA	39
Total output current sunk by sum of all IOs and control pins IIO(PIN)	Absolute maximum ratings	max 80 mA	39
Total output current sourced by sum of all IOs and control pins IIO(PIN)	Absolute maximum ratings	max -80 mA	39
Injected current on FT, FTf and B pins IINJ(PIN)	Absolute maximum limits printed as -5/+0	min -5 · max 0 mA	39
Injected current on TC and RST pin IINJ(PIN)	Absolute maximum magnitude ±5	max 5 mA	39
Injected current on TTa pins IINJ(PIN)	Absolute maximum magnitude ±5	max 5 mA	39
Total injected current (sum of all I/O and control pins) IINJ(PIN)	Absolute maximum magnitude ±25; absolute sum of positive and negative injected currents	max 25 mA	39
Storage temperature range TSTG		min -65 · max 150 °C	39
Maximum junction temperature TJ	Absolute maximum ratings	max 150 °C	39
Internal AHB clock frequency fHCLK		min 0 · max 48 MHz	40
Internal APB clock frequency fPCLK		min 0 · max 48 MHz	40
Standard operating voltage VDD		min 2.4 · max 3.6 V	40
Analog operating voltage VDDA	Must have a potential equal to or higher than VDD	min 2.4 · max 3.6 V	40
Input voltage on TTa pins VIN	Minimum VSS –0.3	max 4 V	40
Input voltage on any other pin VIN	Minimum VSS –0.3	max 4 V	40
Power dissipation at TA = 85 °C for suffix 6 PD	TSSOP20	max 182 mW	40
Ambient temperature for 6 suffix version TA	Maximum power dissipation	min -40 · max 85 °C	40
Ambient temperature for 6 suffix version TA	Low power dissipation; TJ must not exceed TJmax	min -40 · max 105 °C	40
Junction temperature range TJ	6 suffix version	min -40 · max 105 °C	40
Supply current in Run mode, code executing from Flash IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 22 · max 22.8 mA	43
Supply current in Run mode, code executing from Flash IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL on; 24 MHz; maximum at TA = 85 °C	typ 12.2 · max 13.2 mA	43
Supply current in Run mode, code executing from Flash IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 4.4 · max 5.2 mA	43
Supply current in Run mode, code executing from RAM IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 22.2 · max 23.2 mA	43
Supply current in Run mode, code executing from RAM IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL on; 24 MHz; maximum at TA = 85 °C	typ 11.2 · max 12.2 mA	43
Supply current in Run mode, code executing from RAM IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 4 · max 4.5 mA	43
Supply current in Sleep mode, code executing from Flash or RAM IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 14 · max 15.3 mA	43
Supply current in Sleep mode, code executing from Flash or RAM IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL on; 24 MHz; maximum at TA = 85 °C	typ 7.3 · max 7.8 mA	43
Supply current in Sleep mode, code executing from Flash or RAM IDD	VDD = 3.6 V; all peripherals enabled; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 2.6 · max 2.9 mA	43
Supply current in Run mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL on; 48 MHz; maximum at TA = 85 °C	typ 175 · max 215 uA	43
Supply current in Run mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; 8 MHz; maximum at TA = 85 °C	typ 3.9 · max 4.9 uA	43
Supply current in Run mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; 1 MHz; maximum at TA = 85 °C	typ 3.9 · max 4.1 uA	43
Supply current in Run mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 244 · max 275 uA	43
Supply current in Run mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 85 · max 105 uA	43
Supply current in Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL on; 48 MHz; maximum at TA = 85 °C	typ 174 · max 215 uA	43
Supply current in Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; 8 MHz; maximum at TA = 85 °C	typ 3.9 · max 4.9 uA	43
Supply current in Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSE bypass, PLL off; 1 MHz; maximum at TA = 85 °C	typ 3.9 · max 4.9 uA	43
Supply current in Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 244 · max 299 uA	43
Supply current in Sleep mode, code executing from Flash or RAM IDDA	VDDA = 3.6 V; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 85 · max 105 uA	43
Supply current in Stop mode IDD	VDD = VDDA = 3.6 V; regulator in run mode, all oscillators OFF; maximum at TA = 85 °C	typ 19 · max 48 uA	44
Supply current in Stop mode IDD	VDD = VDDA = 3.6 V; regulator in low-power mode, all oscillators OFF; maximum at TA = 85 °C	typ 5 · max 32 uA	44
Supply current in Standby mode IDD	VDD = VDDA = 3.6 V; LSI ON and IWDG ON	typ 2 uA	44
Supply current in Stop mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring ON; regulator in run or low power mode, all oscillators OFF; maximum at TA = 85 °C	typ 2.9 · max 3.5 uA	44
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring ON; LSI ON and IWDG ON	typ 3.3 uA	44
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring ON; LSI OFF and IWDG OFF; maximum at TA = 85 °C	typ 2.8 · max 3.5 uA	44
Supply current in Stop mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring OFF; regulator in run mode or low power, all oscillators OFF	typ 1.7 uA	44
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring OFF; LSI ON and IWDG ON	typ 2.3 uA	44
Supply current in Standby mode IDDA	VDD = VDDA = 3.6 V; VDDA monitoring OFF; LSI OFF and IWDG OFF	typ 1.4 uA	44
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals enabled	typ 23.3 mA	45
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals disabled	typ 11.5 mA	45
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals enabled	typ 4.5 mA	45
Supply current in Run mode from VDD supply IDD	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals disabled	typ 3 mA	45
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals enabled	typ 158 uA	45
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals disabled	typ 158 uA	45
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals enabled	typ 2.43 uA	45
Supply current in Run mode from VDDA supply IDDA	VDD = VDDA = 3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals disabled	typ 2.43 uA	45
Electrostatic discharge voltage (human body model) VESD(HBM)	TA = +25 °C, conforming to JESD22-A114; class 2	max 2000 V	56
Electrostatic discharge voltage (charge device model) VESD(CDM)	TA = +25 °C, conforming to JESD22-C101; class II	max 500 V	56
Thermal resistance junction-ambient JA	TSSOP20; value column	typ 110 °C/W	83
External main supply voltage (including VDDA and VDD) VDD–VSS		min -0.3 · max 4 V	38
Input voltage on TTa pins VIN		max 4 V	38
Input voltage on any other pin VIN		max 4 V	38
Total current into sum of all VDD_x and VDDSDx power lines (source) IVDD		max 120 mA	39
Total current out of sum of all VSS_x and VSSSD ground lines (sink) IVSS		max -120 mA	39
Maximum current into each VDD_x or VDDSDx power pin (source) IVDD(PIN)		max 100 mA	39
Maximum current out of each VSS_x or VSSSD ground pin (sink) IVSS(PIN)		max -100 mA	39
Output current sunk by any I/O and control pin IIO(PIN)		max 25 mA	39
Output current source by any I/O and control pin IIO(PIN)		max -25 mA	39
Total output current sunk by sum of all IOs and control pins IIO(PIN)		max 80 mA	39
Total output current sourced by sum of all IOs and control pins IIO(PIN)		max -80 mA	39
Maximum junction temperature TJ		max 150 °C	39
Input voltage on TTa pins VIN		max 4 V	40
Input voltage on any other pin VIN		max 4 V	40
VDD rise time rate tVDD		min 0 us/V	41
VDD fall time rate tVDD		min 20 us/V	41
VDDA rise time rate tVDDA		min 0 us/V	41
VDDA fall time rate tVDDA		min 20 us/V	41
Power on/power down reset threshold VPOR/PDR	Falling edge	min 1.8 · typ 1.88 · max 2.06 V	41
Power on/power down reset threshold VPOR/PDR	Rising edge	min 1.84 · typ 1.92 · max 2.1 V	41
PDR hysteresis VPDRhyst		typ 40 mV	41
Reset temporization tRSTTEMPO		min 1.5 · typ 2.5 · max 4.5 ms	41
Internal reference voltage VREFINT	–40 °C < TA < +85 °C	min 1.16 · typ 1.2 · max 1.24 V	41
ADC sampling time when reading the internal reference voltage TS_vrefint		typ 5.1 · max 17.1 us	41
Internal reference voltage spread over the temperature range VREFINT	VDDA = 3 V ±10 mV	max 10 mV	42
Temperature coefficient TCoeff		max 100 ppm/°C	42
Supply current in Run mode, code executing from Flash IDD	All peripherals enabled; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 22 · max 22.8 mA	43
Supply current in Run mode, code executing from Flash IDD	All peripherals enabled; HSI clock, PLL on; 24 MHz; maximum at TA = 85 °C	typ 12.2 · max 13.2 mA	43
Supply current in Run mode, code executing from Flash IDD	All peripherals enabled; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 4.4 · max 5.2 mA	43
Supply current in Run mode, code executing from RAM IDD	All peripherals enabled; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 22.2 · max 23.2 mA	43
Supply current in Run mode, code executing from RAM IDD	All peripherals enabled; HSI clock, PLL on; 24 MHz; maximum at TA = 85 °C	typ 11.2 · max 12.2 mA	43
Supply current in Run mode, code executing from RAM IDD	All peripherals enabled; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 4 · max 4.5 mA	43
Supply current in Sleep mode, code executing from Flash or RAM IDD	All peripherals enabled; HSI clock, PLL on; 48 MHz; maximum at TA = 85 °C	typ 14 · max 15.3 mA	43
Supply current in Sleep mode, code executing from Flash or RAM IDD	All peripherals enabled; HSI clock, PLL on; 24 MHz; maximum at TA = 85 °C	typ 7.3 · max 7.8 mA	43
Supply current in Sleep mode, code executing from Flash or RAM IDD	All peripherals enabled; HSI clock, PLL off; 8 MHz; maximum at TA = 85 °C	typ 2.6 · max 2.9 mA	43
Supply current in Run mode from VDD supply IDD	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals enabled	typ 23.3 mA	45
Supply current in Run mode from VDD supply IDD	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals disabled	typ 11.5 mA	45
Supply current in Run mode from VDD supply IDD	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals enabled	typ 4.5 mA	45
Supply current in Run mode from VDD supply IDD	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals disabled	typ 3 mA	45
Supply current in Run mode from VDDA supply IDDA	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals enabled	typ 158 uA	45
Supply current in Run mode from VDDA supply IDDA	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 48 MHz; peripherals disabled	typ 158 uA	45
Supply current in Run mode from VDDA supply IDDA	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals enabled	typ 2.43 uA	45
Supply current in Run mode from VDDA supply IDDA	VDD=VDDA=3.3 V; HSE crystal clock 8 MHz; fHCLK = 8 MHz; peripherals disabled	typ 2.43 uA	45
I/O current consumption ISW	VDD = 3.3 V; CEXT = 0 pF; C = CINT + CEXT + CS; fSW = 4 MHz	typ 0.18 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 0 pF; C = CINT + CEXT + CS; fSW = 8 MHz	typ 0.37 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 0 pF; C = CINT + CEXT + CS; fSW = 16 MHz	typ 0.76 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 0 pF; C = CINT + CEXT + CS; fSW = 24 MHz	typ 1.39 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 0 pF; C = CINT + CEXT + CS; fSW = 48 MHz	typ 2.188 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 22 pF; C = CINT + CEXT + CS; fSW = 4 MHz	typ 0.49 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 22 pF; C = CINT + CEXT + CS; fSW = 8 MHz	typ 0.94 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 22 pF; C = CINT + CEXT + CS; fSW = 16 MHz	typ 2.38 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 22 pF; C = CINT + CEXT + CS; fSW = 24 MHz	typ 3.99 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 47 pF; C = CINT + CEXT + CS; fSW = 4 MHz	typ 0.81 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 47 pF; C = CINT + CEXT + CS; fSW = 8 MHz	typ 1.7 mA	47
I/O current consumption ISW	VDD = 3.3 V; CEXT = 47 pF; fSW = 16 MHz	typ 3.67 mA	47
Wakeup from Stop mode tWUSTOP	VDD = 3.3 V; regulator in run mode; 8-MHz HSI RC oscillator	typ 4.2 · max 5 us	47
Wakeup from Standby mode tWUSTANDBY	VDD = 3.3 V; 8-MHz HSI RC oscillator	typ 50.96 us	47
Wakeup from Sleep mode tWUSLEEP	VDD = 3.3 V; 8-MHz HSI RC oscillator	typ 1.1 us	47
Oscillator frequency fOSC_IN		min 4 · typ 8 · max 32 MHz	50
Feedback resistor RF		typ 200 k	50
HSE current consumption IDD	During startup	max 8.5 mA	50
HSE current consumption IDD	VDD=3.3 V, Rm= 45, CL=10 pF@8 MHz	typ 0.5 mA	50
HSE current consumption IDD	VDD=3.3 V, Rm= 30, CL=20 pF@32 MHz	typ 1.5 mA	50
Oscillator transconductance gm	Startup	min 10 mA/V	50
Startup time tSU(HSE)	VDD is stabilized	typ 2 ms	50
LSE current consumption IDD	LSEDRV[1:0]=00, lower driving capability	typ 0.5 uA	51
LSE current consumption IDD	LSEDRV[1:0]=01, medium low driving capability	typ 0.8 uA	51
LSE current consumption IDD	LSEDRV[1:0]=10, medium high driving capability	typ 1.1 uA	51
LSE current consumption IDD	LSEDRV[1:0]=11, higher driving capability	typ 1.4 uA	51
Oscillator transconductance gm	LSEDRV[1:0]=00, lower driving capability	min 5 uA/V	51
Oscillator transconductance gm	LSEDRV[1:0]=01, medium low driving capability	min 8 uA/V	51
Oscillator transconductance gm	LSEDRV[1:0]=10, medium high driving capability	min 15 uA/V	51
Oscillator transconductance gm	LSEDRV[1:0]=11, higher driving capability	min 25 uA/V	51
Startup time tSU(LSE)	VDD is stabilized	typ 2 s	51
Frequency fHSI	VDDA = 3.3 V, TA = –40 to 85 °C	typ 8 MHz	52
HSI user trimming step TRIM	VDDA = 3.3 V, TA = –40 to 85 °C	max 1 %	52
Duty cycle DuCy(HSI)	VDDA = 3.3 V, TA = –40 to 85 °C	min 45 · max 55 %	52
Accuracy of the HSI oscillator (factory calibrated) ACCHSI	TA = –40 to 85 °C; VDDA = 3.3 V; with user calibration	typ 5 %	52
Accuracy of the HSI oscillator (factory calibrated) ACCHSI	TA = 25 °C; VDDA = 3.3 V; with user calibration	typ 1 %	52
HSI oscillator startup time tsu(HSI)	VDDA = 3.3 V, TA = –40 to 85 °C	min 1 · max 2 us	52
HSI oscillator power consumption IDDA(HSI)	VDDA = 3.3 V, TA = –40 to 85 °C	typ 80 uA	52
Frequency fHSI14	VDDA = 3.3 V, TA = –40 to 85 °C	typ 14 MHz	53
HSI14 user-trimming step TRIM	VDDA = 3.3 V, TA = –40 to 85 °C	max 1 %	53
Duty cycle DuCy(HSI14)	VDDA = 3.3 V, TA = –40 to 85 °C	min 45 · max 55 %	53
Accuracy of the HSI14 oscillator (factory calibrated) ACCHSI14	VDDA = 3.3 V, TA = –40 to 85 °C	typ 5 %	53
HSI14 oscillator startup time tsu(HSI14)	VDDA = 3.3 V, TA = –40 to 85 °C	min 1 · max 2 us	53
HSI14 oscillator power consumption IDDA(HSI14)	VDDA = 3.3 V, TA = –40 to 85 °C	typ 100 uA	53
Frequency fLSI	VDDA = 3.3 V, TA = –40 to 85 °C	min 30 · typ 40 · max 50 kHz	53
LSI oscillator startup time tsu(LSI)	VDDA = 3.3 V, TA = –40 to 85 °C	max 85 us	53
LSI oscillator power consumption IDDA(LSI)	VDDA = 3.3 V, TA = –40 to 85 °C	typ 0.75 uA	53
PLL input clock fPLL_IN		min 1 · max 24 MHz	54
PLL input clock duty cycle fPLL_IN		min 40 · max 60 %	54
PLL multiplier output clock fPLL_OUT		min 16 · max 48 MHz	54
PLL lock time tLOCK		max 200 us	54
Cycle-to-cycle jitter JitterPLL		max 300 ps	54
16-bit programming time tprog	TA = –40 to +85 °C	typ 53.5 us	54
Page (1 KB) erase time tERASE	TA = –40 to +85 °C	typ 30 ms	54
Mass erase time tME	TA = –40 to +85 °C	typ 30 ms	54
Supply current IDD	Write mode; TA = –40 to +85 °C	max 10 mA	54
Supply current IDD	Erase mode; TA = –40 to +85 °C	max 12 mA	54
Programming voltage Vprog	TA = –40 to +85 °C	min 2.4 · max 3.6 V	54
Endurance NEND	TA = –40 to +85 °C (6 suffix versions)	min 1 kcycles	54
Data retention tRET	1 kcycle at TA = 85 °C	min 20 Years	54
Electrostatic discharge voltage (human body model) VESD(HBM)	TA = +25 °C, conforming to JESD22-A114; Class 2	max 2000 V	56
Electrostatic discharge voltage (charge device model) VESD(CDM)	TA = +25 °C, conforming to JESD22-C101; Class II	max 500 V	56
Injected current on BOOT0 IINJ	Negative injection; positive injection NA	min 0 mA	57
Injected current on all FT and FTf pins with induced leakage current on adjacent pins less than –5 uA IINJ	Negative injection; positive injection NA	min -5 mA	57
Injected current on all TTa pins with induced leakage current on adjacent pins less than –5 uA IINJ	Negative and positive injection	min -5 · max 5 mA	57
Injected current on all TC and RESET pins with induced leakage current on adjacent pins less than –5 uA IINJ	Negative and positive injection	min -5 · max 5 mA	57
Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOL	IIO = +8 mA; 2.7 V < VDD < 3.6 V	max 0.4 V	60
Output low level voltage for an I/O pin when 5 pins are sunk at the same time VOL	IIO = +20 mA; 2.7 V < VDD < 3.6 V	max 1.3 V	60
Output low level voltage for an I/O pin when 8 pins are sunk at the same time VOL	IIO = +6 mA; 2.4 V < VDD < 2.7 V	max 0.4 V	60
Output low level voltage for an FTf I/O pin in FM+ mode VOLFM+	IIO = +20 mA	max 0.4 V	60
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = x0; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 2 MHz	61
Output high to low level fall time tf(IO)out	OSPEEDRy[1:0] = x0; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 125 ns	61
Output low to high level rise time tr(IO)out	OSPEEDRy[1:0] = x0; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 125 ns	61
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 01; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 10 MHz	61
Output high to low level fall time tf(IO)out	OSPEEDRy[1:0] = 01; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 25 ns	61
Output low to high level rise time tr(IO)out	OSPEEDRy[1:0] = 01; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 25 ns	61
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 11; CL = 30 pF, VDD = 2.7 V to 3.6 V	max 50 MHz	61
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDD = 2.7 V to 3.6 V	max 30 MHz	61
Maximum frequency fmax(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDD = 2.4 V to 2.7 V	max 20 MHz	61
Output high to low level fall time tf(IO)out	OSPEEDRy[1:0] = 11; CL = 30 pF, VDD = 2.7 V to 3.6 V	max 5 ns	61
Output high to low level fall time tf(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDD = 2.7 V to 3.6 V	max 8 ns	61
Output low to high level rise time tr(IO)out	OSPEEDRy[1:0] = 11; CL = 30 pF, VDD = 2.7 V to 3.6 V	max 5 ns	61
Output low to high level rise time tr(IO)out	OSPEEDRy[1:0] = 11; CL = 50 pF, VDD = 2.7 V to 3.6 V	max 8 ns	61
Maximum frequency fmax(IO)out	FM+ configuration; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 2 MHz	61
Output high to low level fall time tf(IO)out	FM+ configuration; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 12 ns	61
Output low to high level rise time tr(IO)out	FM+ configuration; CL = 50 pF, VDD = 2.4 V to 3.6 V	max 34 ns	61
Pulse width of external signals detected by the EXTI controller tEXTIpw		min 10 ns	61
Analog supply voltage for ADC ON VDDA		min 2.4 · max 3.6 V	64
ADC clock frequency fADC		min 0.6 · max 14 MHz	64
Sampling rate fS		min 0.05 · max 1 MHz	64
External trigger frequency fTRIG	fADC = 14 MHz	max 823 kHz	64
External trigger frequency fTRIG		max 17 1/fADC	64
Conversion voltage range VAIN	Maximum VDDA	min 0 V	64
External input impedance RAIN	See Equation 1 and Table 49 for details	max 50 k	64
Sampling switch resistance RADC		max 1 k	64
Internal sample and hold capacitor CADC		max 8 pF	64
Calibration time tCAL	fADC = 14 MHz	typ 5.9 us	64
Calibration time tCAL		typ 83 1/fADC	64
Trigger conversion latency tlatr	fADC = fPCLK/2 = 14 MHz	typ 0.196 us	64
Trigger conversion latency tlatr	fADC = fPCLK/2	typ 5.5 1/fPCLK	64
Trigger conversion latency tlatr	fADC = fPCLK/4 = 12 MHz	typ 0.219 us	64
Trigger conversion latency tlatr	fADC = fPCLK/4	typ 10.5 1/fPCLK	64
Trigger conversion latency tlatr	fADC = fHSI14 = 14 MHz	min 0.188 · max 0.259 us	64
ADC jitter on trigger conversion JitterADC	fADC = fHSI14	typ 1 1/fHSI14	64
Sampling time tS	fADC = 14 MHz	min 0.107 · max 17.1 us	64
Sampling time tS		min 1.5 · max 239.5 1/fADC	64
Power-up time tSTAB		min 0 · typ 0 · max 1 us	64
Total conversion time (including sampling time) tCONV	fADC = 14 MHz	min 1 · max 18 us	64
Total conversion time (including sampling time) tCONV	tS for sampling +12.5 for successive approximation	min 14 · max 252 1/fADC	64
RAIN max RAIN	Ts = 1.5 cycles; tS = 0.11 us	max 0.4 k	65
RAIN max RAIN	Ts = 7.5 cycles; tS = 0.54 us	max 5.9 k	65
RAIN max RAIN	Ts = 13.5 cycles; tS = 0.96 us	max 11.4 k	65
RAIN max RAIN	Ts = 28.5 cycles; tS = 2.04 us	max 25.2 k	65
RAIN max RAIN	Ts = 41.5 cycles; tS = 2.96 us	max 37.2 k	65
RAIN max RAIN	Ts = 55.5 cycles; tS = 3.96 us	max 50 k	65
Total unadjusted error ET	fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C; after internal calibration	typ 3.3 · max 4 LSB	65
Offset error EO	fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C; after internal calibration	typ 1.9 · max 2.8 LSB	65
Gain error EG	fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C; after internal calibration	typ 2.8 · max 3 LSB	65
Differential linearity error ED	fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C; after internal calibration	typ 0.7 · max 1.3 LSB	65
Integral linearity error EL	fPCLK = 48 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.7 V to 3.6 V, TA = −40 to 85 °C; after internal calibration	typ 1.2 · max 1.7 LSB	65
Thermal resistance junction-ambient JA	TSSOP20	typ 110 °C/W	83

Pins, by the datasheet

4 NRST: Device reset input and internal reset output, active low. · p. 26
5 VDDA: Analog power supply. · p. 26
6 PA0: GPIO with ADC_IN0, RTC_TAMP2 and WKUP1 functions. · p. 26
7 PA1: GPIO with ADC_IN1 and EVENTOUT functions. · p. 26
8 PA2: GPIO with ADC_IN2 function. · p. 26
9 PA3: GPIO with ADC_IN3 function. · p. 26
10 PA4: GPIO with SPI1_NSS, TIM14_CH1 and ADC_IN4 functions. · p. 27
11 PA5: GPIO with SPI1_SCK and ADC_IN5 functions. · p. 27
12 PA6: GPIO with SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT and ADC_IN6 functions. · p. 27
13 PA7: GPIO with SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT and ADC_IN7 functions. · p. 27
14 PB1: GPIO with TIM3_CH4, TIM14_CH1, TIM1_CH3N and ADC_IN9 functions. · p. 27
16 VDD: Digital power supply. · p. 27
17 PA9: GPIO with USART1_TX and TIM1_CH2 functions. · p. 28
18 PA10: GPIO with USART1_RX, TIM1_CH3 and TIM17_BKIN functions. · p. 28
1 BOOT0: Boot memory selection. · p. 29
15 VSS: Ground. · p. 30

Parameters

ADC (Bit): 12bit
CPU Core: ARM Cortex-M0
CPU Maximum Speed: 48MHz
Core Size: 32 Bit
Current - Supply: 23.46mA
Junction Temperature(Max): 105℃
Number of I/O: 15
Operating Temperature: -40℃~+105℃
Oscillator Type: Built-in
Output Current per Pin(Max): 25mA
Program Memory Type: FLASH
Program Storage Size: 16KB
RAM Size: 4KB
Standby Current: 5.3uA
Thermal Resistance(Junction to Ambient): 110℃/W
Voltage - Supply: 2.4V~3.6V
Voltage - Supply(Absolute Max): 4V

Order codes

STM32F030F4P6LCSC C32908
STM32F030F4P6TRLCSC C89040

Pinout

The pins of the STM32F030F4P6
Pin	Name	Type
1	BOOT0	Input
2	PF0	Input/output
3	PF1	Input/output
4	NRST	Input
5	VDDA	Power in
6	PA0	Input/output
7	PA1	Input/output
8	PA2	Input/output
9	PA3	Input/output
10	PA4	Input/output
11	PA5	Input/output
12	PA6	Input/output
13	PA7	Input/output
14	PB1	Input/output
15	VSS	Power in
16	VDD	Power in
17	PA9	Input/output
18	PA10	Input/output
19	PA13	Input/output
20	PA14	Input/output

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Open-source boards using it

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Parts like it

Questions

Is there a KiCad symbol and footprint for the STM32F030F4P6?

Yes. The symbol is MCU_ST_STM32F0:STM32F030F4Px and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the STM32F030F4P6?

TSSOP-20, with 20 pins. Its footprint is drawn on this page.

Where is the STM32F030F4P6 datasheet?

STMicroelectronics publishes it: the Datasheet link on this page opens it.

Where can I order the STM32F030F4P6?

JLCPCB lists it as part C89040, with 59,987 in stock; the sellers' links on this page open their listings.

What can replace the STM32F030F4P6?

Parts like it in the library: the CH32V003F4P6 by WCH (Nanjing Qinheng Microelectronics), the STM32G030F6P6 by STMicroelectronics, the STM32F042F4P6 by STMicroelectronics and the STM32F042F6P6 by STMicroelectronics. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the STM32F030F4P6?

41 boards in 30 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

STM32F030F4P6

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Open-source boards using it

Hexdump

Brew buddy hardware

Lcr 2

FlockOne

Signalgen

Stm32f0..f breakout

Gener5351

PioneerBMWInterface

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