2 layers26.2 × 26.2 mm
Microcontroller
bountylabs/blocks-with-screens
It's a Twitterversary block, but with a screen and the internet.
15 parts32MIT
Overview
The LIS2DW12 is an accelerometer made by STMicroelectronics in a LGA-12(2x2) package with 12 pins. -40℃~+85℃ 1.62V~3.6V 16bit 50nA Accelerometer Motion event detection SPI、I2C X,Y,Z ±16g LGA-12(2x2) Accelerometers ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Cloud:LIS2DUX12TR, from EasyEDA) and its footprint (4ms_Package_QFP:LGA-12_2x2mm_P0.5mm, from KiCad's library), ready for a KiCad board. 31,837 are in stock at JLCPCB (part C189624). 14 open-source boards in 13 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
8- Supply, least
- 1.62 V · Vdd, recommended operating min · p. 13
- Supply, most
- 3.6 V · Vdd, recommended operating max · p. 13
- Supply, absolute maximum
- 4.8 V · Vdd, absolute max · p. 18
- Works from
- -40 °C · Operating temperature min · p. 18
- Works up to
- 85 °C · Operating temperature max · p. 18
- Takes working
- 90 µA · High-Performance Mode typical, Vdd=1.8 V, low-noise disabled, ODR=100 Hz · p. 20
- Takes asleep
- 50 nA · Power-down typical, Vdd=1.8 V · p. 13
- A pin gives at most
- 4 mA · Digital pad source/sink max guaranteeing VOH and VOL · p. 13
What it is and has
9- Accelerometer
- High-performance ultra-low-power 3-axis · p. 1
- Full scale
- ±2g/±4g/±8g/±16g · p. 1
- Digital interface
- High-speed I2C/SPI · p. 1
- Data output
- 16-bit · p. 1
- Temperature sensor
- Embedded · p. 1
- FIFO
- 32 levels · p. 1
- Self-test
- Embedded · p. 1
- IO supply
- Independent · p. 1
- Compliance
- ECOPACK®, RoHS and Green · p. 1
Around it
1- res not specified
- between SCL and Vdd_IO; External pull-up required for I2C. · p. 33
Specifications
50| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage Vdd | min 1.62 · typ 1.8 · max 3.6 V | 13 | |
| I/O pins supply voltage Vdd_IO | Maximum Vdd+0.1 V | min 1.62 V | 13 |
| Current consumption in High-Performance Mode IddHR | ODR range 12.5 Hz - 1600 Hz, 14-bit; low-noise setting disabled | typ 90 uA | 13 |
| Current consumption in Low-Power Mode IddLP | ODR 100 Hz; Low-Power Mode 1; low-noise setting disabled | typ 5 uA | 13 |
| Current consumption in Low-Power Mode IddLP | ODR 50 Hz; Low-Power Mode 1; low-noise setting disabled | typ 3 uA | 13 |
| Current consumption in Low-Power Mode IddLP | ODR 12.5 Hz; Low-Power Mode 1; low-noise setting disabled | typ 1 uA | 13 |
| Current consumption in Low-Power Mode IddLP | ODR 1.6 Hz; Low-Power Mode 1; low-noise setting disabled | typ 0.38 uA | 13 |
| Current consumption in power-down Idd_PD | typ 50 nA | 13 | |
| Digital low-level output voltage VOL | IOL = 4 mA | max 0.2 V | 13 |
| SCL clock frequency fSCL | Fast mode plus | min 0 · max 1 MHz | 17 |
| Hold time (repeated) START condition tHD;STA | Fast mode plus | min 260 ns | 17 |
| Low period of the SCL clock tLOW | Fast mode plus | min 500 ns | 17 |
| High period of the SCL clock tHIGH | Fast mode plus | min 260 ns | 17 |
| Setup time for a repeated START condition tSU;STA | Fast mode plus | min 260 ns | 17 |
| Data hold time tHD;DAT | Fast mode plus | min 0 ns | 17 |
| Data setup time tSU;DAT | Fast mode plus | min 50 ns | 17 |
| Rise time of SDA signal trDA | Fast mode plus | max 120 ns | 17 |
| Fall time of SDA signal tfDA | Fast mode plus | max 120 ns | 17 |
| Rise time of SCL signal trCL | Fast mode plus; minimum 20*Vdd/5.5 ns | max 120 ns | 17 |
| Fall time of SCL signal tfCL | Fast mode plus; minimum 20*Vdd/5.5 ns | max 120 ns | 17 |
| Setup time for STOP condition tSU;STO | Fast mode plus | min 260 ns | 17 |
| Capacitive load for each bus line Cb | Fast mode plus | max 550 pF | 17 |
| Data valid time tVD;DAT | Fast mode plus | max 450 ns | 17 |
| Data valid acknowledge time tVD;ACK | Fast mode plus | max 450 ns | 17 |
| Pulse width of spikes that must be suppressed by the input filter tSP | Fast mode plus | min 0 · max 50 ns | 17 |
| SCLH clock frequency fSCLH | High-speed mode | min 0 · max 3.4 MHz | 17 |
| Setup time for a repeated START condition tSU;STA | High-speed mode | min 160 ns | 17 |
| Hold time (repeated) START condition tHD;STA | High-speed mode | min 160 ns | 17 |
| Low period of the SCLH clock tLOW | High-speed mode | min 160 ns | 17 |
| High period of the SCLH clock tHIGH | High-speed mode | min 60 ns | 17 |
| Data setup time tSU;DAT | High-speed mode | min 10 ns | 17 |
| Data hold time tHD;DAT | High-speed mode | min 0 · max 70 ns | 17 |
| Rise time of SCLH signal trCL | High-speed mode | min 10 · max 40 ns | 17 |
| Rise time of SCLH signal after a repeated START condition and after an acknowledge bit trCL1 | High-speed mode | min 10 · max 80 ns | 17 |
| Fall time of SCLH signal tfCL | High-speed mode | min 10 · max 40 ns | 17 |
| Rise time of SDAH signal trDA | High-speed mode | min 10 · max 80 ns | 17 |
| Fall time of SDAH signal tfDA | High-speed mode | min 10 · max 80 ns | 17 |
| Setup time for STOP condition tSU;STO | High-speed mode | min 160 ns | 17 |
| Capacitive load for each bus line Cb | High-speed mode | max 100 pF | 17 |
| Pulse width of spikes that must be suppressed by the input filter tSP | High-speed mode | min 0 · max 10 ns | 17 |
| Supply voltage Vdd | min -0.3 · max 4.8 V | 18 | |
| I/O pins supply voltage Vdd_IO | min -0.3 · max 4.8 V | 18 | |
| Input voltage on any control pin Vin | CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0; maximum Vdd_IO +0.3 V | min -0.3 V | 18 |
| Acceleration (any axis, powered, Vdd = 1.8 V) APOW | 0.5 ms | max 3000 g | 18 |
| Acceleration (any axis, powered, Vdd = 1.8 V) APOW | 0.2 ms | max 10000 g | 18 |
| Acceleration (any axis, unpowered) AUNP | 0.5 ms | max 3000 g | 18 |
| Acceleration (any axis, unpowered) AUNP | 0.2 ms | max 10000 g | 18 |
| Operating temperature range TOP | min -40 · max 85 °C | 18 | |
| Storage temperature range TSTG | min -40 · max 125 °C | 18 | |
| Electrostatic discharge protection ESD | HBM | max 2 kV | 18 |
Pins, by the datasheet
12- 1 SCL/SPC
- I2C serial clock or SPI serial port clock. · p. 18
- 2 CS
- SPI enable and I2C/SPI mode selection; high enables I2C and SPI idle, low enables SPI and disables I2C; internally pulled up. · p. 9
- 3 SDO/SA0
- SPI serial data output or I2C device address least significant bit; internally pulled up. · p. 9
- 4 SDA/SDI/SDO
- I2C serial data, SPI serial data input, or 3-wire serial data output. · p. 18
- 5 NC
- Internally not connected; can be tied to VDD, VDDIO, or GND. · p. 9
- 6 GND
- 0 V supply. · p. 9
- 7 RES
- Connect to GND. · p. 9
- 8 GND
- 0 V supply. · p. 9
- 9 VDD
- Power supply. · p. 9
- 10 VDD_IO
- Power supply for I/O pins. · p. 9
- 11 INT2
- Interrupt pin 2; clock input when selected in single data conversion on demand. · p. 9
- 12 INT1
- Interrupt pin 1. · p. 9
Ordering codes, by the datasheet
2- LIS2DW12
- LGA-12 · Tray; -40 to +85 °C · p. 1
- LIS2DW12TR
- LGA-12 · Tape and reel; -40 to +85 °C · p. 1
Parameters
12- Acceleration Measurement Range (MAX)
- ±16g
- Accelerometer Sensing Axis
- X,Y,Z
- Current - Supply
- 90uA
- Features
- Motion event detection
- Interface
- SPI
- Operating Temperature
- -40℃~+85℃
- Output Bits
- 16bit
- Output Current per Pin(Max)
- 4mA
- Sensor Type
- Accelerometer
- Standby Current
- 50nA
- Voltage - Supply
- 1.62V~3.6V
- Voltage - Supply(Absolute Max)
- 4.8V
Order codes
1- LIS2DW12TRLCSC C189624
Pinout
12| Pin | Name | Type |
|---|---|---|
| 1 | SCL/SPC | Unspecified |
| 2 | CS | Unspecified |
| 3 | SDO/SA0 | Unspecified |
| 4 | SDA/SDI/SDO | Unspecified |
| 5 | NC | Unspecified |
| 6 | GND | Unspecified |
| 7 | RES | Unspecified |
| 8 | GND | Unspecified |
| 9 | VDD | Unspecified |
| 10 | VDDIO | Unspecified |
| 11 | INT2 | Unspecified |
| 12 | INT1 | Unspecified |
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<iframe src="https://pcbkit.io/embed/parts/st/LIS2DW12" title="LIS2DW12 in PCBKit" width="100%" height="480" style="border:0;border-radius:12px" allow="fullscreen" loading="lazy"></iframe><img src="https://pcbkit.io/embed/parts/st/LIS2DW12.jpg" alt="LIS2DW12" width="1200" height="900">[](https://pcbkit.io/parts/st/LIS2DW12)Questions
Is there a KiCad symbol and footprint for the LIS2DW12?
Yes. The symbol is EasyEDA_Cloud:LIS2DUX12TR and the footprint 4ms_Package_QFP:LGA-12_2x2mm_P0.5mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the LIS2DW12?
LGA-12(2x2), with 12 pins. Its footprint is drawn on this page.
Where is the LIS2DW12 datasheet?
STMicroelectronics publishes it: the Datasheet link on this page opens it.
Where can I order the LIS2DW12?
JLCPCB lists it as part C189624, with 31,837 in stock; the sellers' links on this page open their listings.
What can replace the LIS2DW12?
Parts like it in the library: the SC7A20HTR by Hangzhou Silan Microelectronics, the LSM303AGR by STMicroelectronics, the QMA6100P by QST and the KX134-1211 by ROHM Semiconductor. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the LIS2DW12?
14 boards in 13 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
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