4 layers48 × 32 mm
FlatSat
Pwnsat/FlatSat
Flatsat v1.0 is a hardware based platform for aerospace cybersecurity research
106 parts575GPL-2.0
SX1262IMLTRT
SEMTECHExtended
-148dBm -40℃~+85℃ 1.8V~3.7V 150MHz~960MHz 22dBm 300Kbps 32mA 4.2mA ISM SPI Supports software reset、Power-on reset function、Supports RSSI function transceiver QFN-24-EP(4x4) RF Transceiver ICs ROHS
- Part id
- semtech/SX1262IMLTRT
- Category
- RF Transceiver ICs
- Package
- QFN-24-EP(4x4)
- Pins
- 25
- In stock
- 39,193 at JLCPCB (C191341)
- Used on
- 73 open-source boards
Overview
The SX1262IMLTRT is a RF Transceiver IC made by SEMTECH in a QFN-24-EP(4x4) package with 25 pins. -148dBm -40℃~+85℃ 1.8V~3.7V 150MHz~960MHz 22dBm 300Kbps 32mA 4.2mA ISM SPI Supports software reset、Power-on reset function、Supports RSSI function transceiver QFN-24-EP(4x4) RF Transceiver ICs ROHS.
PCBKit's library has its KiCad symbol (RF:SX1262IMLTRT, from KiCad's library) and its footprint (Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm, from KiCad's library), ready for a KiCad board. 39,193 are in stock at JLCPCB (part C191341). 73 open-source boards in 59 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
11- Supply, least
- 1.8 V · VBAT, recommended operating min · p. 14
- Supply, most
- 3.7 V · VBAT, recommended operating max · p. 14
- Supply, absolute maximum
- 3.9 V · VBAT, absolute max · p. 14
- Works from
- -40 °C · Temperature under bias min · p. 14
- Works up to
- 85 °C · Temperature under bias max · p. 14
- Takes working
- 4.2 mA · VBAT tied to VBAT_IO, receive FSK 4.8 kb/s, DC-DC, typical · p. 16
- Takes at most
- 118 mA · SX1262 transmit +22 dBm, 868/915 MHz, typical · p. 17
- Takes asleep
- 160 nA · SLEEP with cold start, all blocks off, typical · p. 16
- Takes asleep
- 600 nA · SLEEP with warm start, configuration retained, typical · p. 16
- Takes asleep
- 1.2 µA · SLEEP with warm start, configuration retained and RC64k, typical · p. 16
- Data rate, most
- 300 kbit/s · FSK bit rate max, minimum modulation index 0.5 · p. 18
What it is and has
3- Modulation
- LoRa and (G)FSK · p. 1
- Frequency coverage
- 150 MHz to 960 MHz · p. 1
- Package
- QFN 24, Pb-free, Halogen free, RoHS/WEEE compliant · p. 2
Around it
1- ind 15 μH
- between pin 7 and pin 9; For DC-DC operation; preferred shielded inductor with low series resistance and resonance well above switching frequency. Selection guidance: DCR maximum 2 ohms, Idc minimum 100 mA, frequency minimum 20 MHz. · p. 32
Specifications
106| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Class 2 of ANSI/ESDA/JEDEC Standard JS-001-2014 (Human Body Model) ESD_HBM | max 2 kV | 14 | |
| ESD Charged Device Model, JEDEC standard JESD22-C101D, class III ESD_CDM | max 1000 V | 14 | |
| Latch-up, JEDEC standard JESD78 B, class I level A LU | max 100 mA | 14 | |
| Supply voltage, applies to VBAT and VBAT_IO VDDmr | min -0.5 · max 3.9 V | 14 | |
| Temperature Tmr | min -55 · max 125 °C | 14 | |
| RF Input level Pmr | max 10 dBm | 14 | |
| Supply voltage, applies to VBAT and VBAT_IO VDDop | min 1.8 · max 3.7 V | 14 | |
| Temperature under bias Top | min -40 · max 85 °C | 14 | |
| Load capacitance on digital ports Clop | max 20 pF | 14 | |
| RF Input power ML | max 0 dBm | 14 | |
| Crystal oscillator frequency FXOSC | typ 32 MHz | 15 | |
| Crystal load capacitance CLOAD | typ 10 pF | 15 | |
| Crystal shunt capacitance C0XTAL | min 0.3 · typ 0.6 · max 2 pF | 15 | |
| Crystal series resistance RSXTAL | typ 30 · max 60 | 15 | |
| Crystal motional capacitance CMXTAL | min 1.3 · typ 1.89 · max 2.5 fF | 15 | |
| Drive level DRIVE | max 100 W | 15 | |
| OFF mode (SLEEP mode with cold start) IDDOFF | All blocks off; VBAT_IO = VBAT = 3.3 V | typ 160 nA | 16 |
| SLEEP mode (SLEEP mode with warm start) IDDSL | Configuration retained; VBAT_IO = VBAT = 3.3 V | typ 600 nA | 16 |
| SLEEP mode (SLEEP mode with warm start) IDDSL | Configuration retained + RC64k; VBAT_IO = VBAT = 3.3 V | typ 1.2 A | 16 |
| STDBY_RC mode IDDSBR | RC13M, XOSC OFF; VBAT_IO = VBAT = 3.3 V | typ 0.6 mA | 16 |
| STDBY_XOSC mode IDDSBX | XOSC ON; VBAT_IO = VBAT = 3.3 V | typ 0.8 mA | 16 |
| Synthesizer mode IDDFS | DC-DC mode used; VBAT_IO = VBAT = 3.3 V | typ 2.1 mA | 16 |
| Synthesizer mode IDDFS | LDO mode used; VBAT_IO = VBAT = 3.3 V | typ 3.55 mA | 16 |
| Receive mode DC-DC mode used IDDRX | FSK 4.8 kb/s; VBAT_IO = VBAT = 3.3 V | typ 4.2 mA | 16 |
| Receive mode DC-DC mode used IDDRX | LoRa® 125 kHz; VBAT_IO = VBAT = 3.3 V | typ 4.6 mA | 16 |
| Receive mode DC-DC mode used IDDRX | Rx Boosted, FSK 4.8 kb/s; VBAT_IO = VBAT = 3.3 V | typ 4.8 mA | 16 |
| Receive mode DC-DC mode used IDDRX | Rx Boosted, LoRa® 125 kHz; VBAT_IO = VBAT = 3.3 V | typ 5.3 mA | 16 |
| Receive mode DC-DC mode used IDDRX | LoRa® 125 kHz, VBAT = 1.8 V | typ 8.2 mA | 16 |
| Receive mode LDO mode used IDDRX | FSK 4.8 kb/s; VBAT_IO = VBAT = 3.3 V | typ 8 mA | 16 |
| Receive mode LDO mode used IDDRX | LoRa® 125 kHz; VBAT_IO = VBAT = 3.3 V | typ 8.8 mA | 16 |
| Receive mode LDO mode used IDDRX | Rx Boosted, FSK 4.8 kb/s; VBAT_IO = VBAT = 3.3 V | typ 9.3 mA | 16 |
| Receive mode LDO mode used IDDRX | Rx Boosted, LoRa® 125 kHz; VBAT_IO = VBAT = 3.3 V | typ 10.1 mA | 16 |
| Transmit current IDDTX | SX1262; 868/915 MHz; PA match +22 dBm; power output +22 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 118 mA | 17 |
| Transmit current IDDTX | SX1262; 868/915 MHz; PA match +22 dBm; power output +20 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 102 mA | 17 |
| Transmit current IDDTX | SX1262; 868/915 MHz; PA match +22 dBm; power output +17 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 95 mA | 17 |
| Transmit current IDDTX | SX1262; 868/915 MHz; PA match +22 dBm; power output +14 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 90 mA | 17 |
| Transmit current IDDTX | SX1262; 868/915 MHz; +20 dBm / optimal settings; power output +20 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 84 mA | 17 |
| Transmit current IDDTX | SX1262; 868/915 MHz; +17 dBm / optimal settings; power output +17 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 58 mA | 17 |
| Transmit current IDDTX | SX1262; 868/915 MHz; +14 dBm / optimal settings; power output +14 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 45 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; PA match +22 dBm; power output +22 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 107 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; PA match +22 dBm; power output +20 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 90 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; PA match +22 dBm; power output +17 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 75 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; PA match +22 dBm; power output +14 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 63 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; +20 dBm / optimal settings; power output +20 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 65 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; +17 dBm / optimal settings; power output +17 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 42 mA | 17 |
| Transmit current IDDTX | SX1262; 434/490 MHz; +14 dBm / optimal settings; power output +14 dBm; VBAT = 3.3 V; DC-DC core, PA supplied from VBAT | typ 32 mA | 17 |
| Synthesizer frequency step FSTEP | - | typ 0.95 Hz | 18 |
| Synthesizer phase noise (for 868 / 915 MHz) PHN | 1 kHz offset | typ -75 dBc/Hz | 18 |
| Synthesizer phase noise (for 868 / 915 MHz) PHN | 10 kHz offset | typ -95 dBc/Hz | 18 |
| Synthesizer phase noise (for 868 / 915 MHz) PHN | 100 kHz offset | typ -100 dBc/Hz | 18 |
| Synthesizer phase noise (for 868 / 915 MHz) PHN | 1MHz offset | typ -120 dBc/Hz | 18 |
| Synthesizer phase noise (for 868 / 915 MHz) PHN | 10 MHz offset | typ -135 dBc/Hz | 18 |
| Synthesizer wake-up time TS_FS | From STDBY_XOSC mode | typ 40 s | 18 |
| Synthesizer hop time TS_HOP | 10 MHz step | typ 30 s | 18 |
| Crystal oscillator wake-up time TS_OSC | from STDBY_RC | typ 150 s | 18 |
| Bit rate, FSK BR_F | Programmable; Minimum modulation index is 0.5 | min 0.6 · max 300 kb/s | 18 |
| Frequency deviation, FSK FDA | Programmable; FDA + BR_F / 2 250 kHz | min 0.6 · max 200 kHz | 18 |
| Bit rate LoRa® BR_L | Min. for SF12, BW_L = 7.8 kHz; Max. for SF5, BW_L = 500 kHz | min 0.018 · max 62.5 kb/s | 18 |
| Signal BW, LoRa® BW_L | Programmable | min 7.8 · max 500 kHz | 18 |
| Spreading factor for LoRa® SF | Programmable, chips/symbol = 2^SF | min 5 · max 12 - | 18 |
| Regulated voltage range for TCXO voltage supply VTCXO | Min/Max values in typical conditions, Typ value for default setting; VDDop > VTCXO + 200 mV | min 1.6 · typ 1.7 · max 3.3 V | 18 |
| Load current for TCXO regulator ILTCXO | typ 1.5 · max 4 mA | 18 | |
| Start-up time for TCXO regulator TSVTCXO | From enable to regulated voltage within 25 mV from target | max 100 s | 18 |
| Current consumption of the TCXO regulator IDDTCXO | Quiescent current | max 70 A | 18 |
| Current consumption of the TCXO regulator IDDTCXO | Relative to load current | typ 1 · max 2 % | 18 |
| Amplitude voltage for external TCXO applied toXTA pin ATCXO | provided through a 220 resistor in series with a 10 pF capacitance | min 0.4 · typ 0.6 · max 1.2 Vpk-pk | 18 |
| Sensitivity 2-FSK RXS_2FB | RX Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BR_F = 0.6 kb/s, FDA = 0.8 kHz, BW_F = 4 kHz | typ -125 dBm | 19 |
| Sensitivity 2-FSK RXS_2FB | RX Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BR_F = 1.2 kb/s, FDA = 5 kHz, BW_F = 20 kHz | typ -123 dBm | 19 |
| Sensitivity 2-FSK RXS_2FB | RX Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BR_F = 4.8 kb/s, FDA = 5 kHz, BW_F = 20 kHz | typ -118 dBm | 19 |
| Sensitivity 2-FSK RXS_2FB | RX Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BR_F = 38.4 kb/s, FDA = 40 kHz, BW_F = 160 kHz | typ -109 dBm | 19 |
| Sensitivity 2-FSK RXS_2FB | RX Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BR_F = 250 kb/s, FDA = 125 kHz, BW_F = 500 kHz | typ -104 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 10.4 kHz, SF = 7 | typ -134 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 10.4 kHz, SF = 12 | typ -148 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 125 kHz, SF = 7 | typ -124 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 125 kHz, SF = 12 | typ -137 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 250 kHz, SF = 7 | typ -121 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 500 kHz, SF = 7 | typ -117 dBm | 19 |
| Sensitivity LoRa® RXS_LB | Rx Boosted gain, split RF paths for Rx and Tx, RF switch insertion loss excluded; BW_L = 500 kHz, SF = 12 | typ -129 dBm | 19 |
| Sensitivity 2-FSK RXS_2F | Rx Power Saving gain with direct tie connection between Rx and Tx; BR_F = 4.8 kb/s, FDA = 5 kHz, BW_F = 20 kHz | typ -115 dBm | 19 |
| Sensitivity LoRa® RXS_L | Rx Power Saving gain with direct tie connection between Rx and Tx; BW_L = 125 kHz, SF = 12 | typ -133 dBm | 19 |
| Co-channel rejection, FSK CCR_F | typ -9 dB | 19 | |
| Co-channel rejection, LoRa® CCR_L | SF = 7 | typ 5 dB | 19 |
| Co-channel rejection, LoRa® CCR_L | SF = 12 | typ 19 dB | 19 |
| Adjacent channel rejection, FSK ACR_F | Offset = +/- 50 kHz | typ 45 dB | 19 |
| Adjacent channel rejection, LoRa® ACR_L | Offset = +/- 1.5 x BW_L; BW_L = 125 kHz, SF = 7 | typ 60 dB | 19 |
| Adjacent channel rejection, LoRa® ACR_L | Offset = +/- 1.5 x BW_L; BW_L = 125 kHz, SF = 12 | typ 72 dB | 19 |
| Maximum RF output power TXOP | SX1262; Highest power step setting | typ 22 dBm | 21 |
| RF output power drop versus supply voltage TXDRP | SX1262, +22 dBm, VBAT = 2.7 V | typ 2 dB | 21 |
| RF output power drop versus supply voltage TXDRP | SX1262, +22 dBm, VBAT = 2.4 V | typ 3 dB | 21 |
| RF output power drop versus supply voltage TXDRP | SX1262, +22 dBm, VBAT = 1.8 V | typ 6 dB | 21 |
| Power amplifier ramping time TXRMP | Programmable | min 10 · max 3400 s | 21 |
| Input Low Voltage VIL | Maximum = 0.3*VBAT_IO; NRESET and DIO3 are referred to VBAT. | min -0.3 V | 21 |
| Input Low Voltage for pin NRESET VIL_N | Maximum = 0.2*VBAT | min -0.3 V | 21 |
| Output Low Voltage VOL | Imax = 2.5 mA; maximum = 0.1*VBAT_IO. NRESET and DIO3 are referred to VBAT. | min 0 V | 21 |
| Digital input leakage current Ileak | NSS, MOSI, SCK | min -1 · max 1 A | 21 |
| NSS falling edge to SCK setup time t1 | Maximum load capacitance 10 pF | min 32 ns | 50 |
| SCK period t2 | Maximum load capacitance 10 pF | min 62.5 ns | 50 |
| SCK high time t3 | Maximum load capacitance 10 pF | min 31.25 ns | 50 |
| MOSI to SCK hold time t4 | Maximum load capacitance 10 pF | min 5 ns | 50 |
| MOSI to SCK setup time t5 | Maximum load capacitance 10 pF | min 5 ns | 50 |
| NSS falling to MISO delay t6 | Maximum load capacitance 10 pF | min 0 · max 15 ns | 50 |
| SCK falling to MISO delay, t7 | Maximum load capacitance 10 pF | min 0 · max 15 ns | 50 |
| SCK to NSS rising edge hold time t8 | Maximum load capacitance 10 pF | min 31.25 ns | 50 |
| NSS high time t9 | Maximum load capacitance 10 pF | min 125 ns | 50 |
| NSS falling edge to SCK setup time when switching from SLEEP to STDBY_RC mode t10 | Maximum load capacitance 10 pF | min 100 s | 50 |
| NSS falling to MISO delay when switching from SLEEP to STDBY_RC mode t11 | Maximum load capacitance 10 pF | min 0 · max 150 s | 50 |
Ordering codes, by the datasheet
2- SX1262IMLTRT
- QFN 24 · SX1262; Tape & Reel; minimum order quantity 3’000 pieces · p. 2
- SX1261IMLTRT
- QFN 24 · SX1261; Tape & Reel; minimum order quantity 3’000 pieces · p. 2
- 4 layers68.8 × 90.3 mm
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Questions
Is there a KiCad symbol and footprint for the SX1262IMLTRT?
Yes. The symbol is RF:SX1262IMLTRT and the footprint Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the SX1262IMLTRT?
QFN-24-EP(4x4), with 25 pins. Its footprint is drawn on this page.
Where is the SX1262IMLTRT datasheet?
SEMTECH publishes it: the Datasheet link on this page opens it.
Where can I order the SX1262IMLTRT?
JLCPCB lists it as part C191341, with 39,193 in stock; the sellers' links on this page open their listings.
What can replace the SX1262IMLTRT?
Parts like it in the library: the SX1261IMLTRT by SEMTECH. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the SX1262IMLTRT?
73 boards in 59 repositories on GitHub; the most starred are listed on this page, with their KiCad files.