2 layers330 × 100 mm Phase3-backplane, the printed circuit board in 3D

Phase3-backplane

A modular, rack-style DC power supply: up to 8 hot-pluggable 600 W buck modules on a shared DC input bus, coordinated by a central manager over CAN.

Open in PCBKit

Size: 330 × 100 mm
Copper layers: 2
Thickness: 1.6 mm
Parts: 39
Nets: 31
Pads: 161
Tracks, vias: 182, 61
Pours: 7
Routed: Yes
KiCad: KiCad 10.0 (file 20260206)
Created: 13 Jul 2026
Updated: 20 Oct 2026

Overview

Phase3-backplane is an open-source printed circuit board by udaravima, from the udaravima/Lab_Bench repository on GitHub, published under the GPL-3.0 licence. It is a 2-layer board of 330 × 100 mm with 39 parts on 31 nets, routed with 182 tracks and 61 vias.

It is built around the SMBJ33A. Its parts include 20 connectors, 3 capacitors, 3 resistors, 1 IC and 1 diode. It belongs with the power boards of this library.

Main components

SMBJ33A
DO-214AA(SMB)-55℃~+150℃ 11.26A@10/1000us 33V 40.6V 53.3V 5uA 600W@10/1000us IEC 61000-4-2 TVS Unidirectional DO-214AA(SMB) ESD and Surge Protection (TVS/ESD) ROHShongjiachengESD And Surge Protection (TVS/ESD)

README

README.md

Lab_Bench — Multi-Channel Modular Power Supply

A modular, rack-style DC power supply: up to 8 hot-pluggable 600 W buck modules on a shared DC input bus, coordinated by a central manager over CAN. Each channel is a self-contained analog CV/CC supply with bench-grade precision, usable for lab work, bulk DC power, and battery charging.

Headline specification

Parameter	Value
Input bus	24–30 V DC nominal (12 V tolerated, output ceiling drops with it)
Channels	1–8, hot-pluggable, slot-addressed
Per-channel output	0 … (V_in − 2 V), 0–30 A, 600 W envelope (first limit binds)
Regulation	Analog CV/CC (diode-OR min-selector), firmware never in the loop
Setpoint resolution	~0.5 mV / ≤0.8 mA (16-bit DAC, per-module calibration)
Readback	20-bit INA228, ±0.05 % class
Comms	CAN 2.0B @ 500 kbit/s, heartbeat-supervised
Scaling	Channels parallel into droop-share groups (firmware feature)
Grounding	All outputs share input ground — parallel OK, no series stacking
Global limits	Manager-enforced total power budget + hardwired E-stop line

Documentation index

Doc	Contents
docs/01-system-architecture.md	Topology, backplane, grounding, power budget
docs/02-module-design.md	600 W module: power stage, CV/CC loop, sensing, MCU
docs/03-can-protocol.md	Bus parameters, ID map, payloads, fault semantics
docs/04-protection-matrix.md	Every fault: detection, response, latching, recovery
docs/05-build-plan.md	Phased build with exit criteria (150 W proto → 8-ch rack)
docs/06-phase1-circuit-design.md	Worked component values for the 150 W prototype
docs/07-module-firmware.md	STM32G431 firmware architecture, pin map, bring-up
docs/08-phase2-circuit-design.md	Worked component values for the 600 W module (LM5143 + LM5069)
docs/09-phase3-circuit-design.md	Backplane + ESP32-S3 manager design (slots, E-stop chain, bus metering, UI)
docs/10-manager-firmware.md	Manager firmware architecture (host-tested core + ESP-IDF shell)
docs/11-build-guide.md	How to build one: ordering, assembly, firmware, first power-up
docs/12-phase1-bench-tests.md	Phase-1 bench test procedure against the exit criteria (+ results template)
hardware/SOURCING.md	LCSC-first part sourcing, prices, order-early list
HANDOVER.md	Session handover: state, decisions, gotchas, next steps
hardware/phase1-module/tools/README.md	Schematic/PCB generation + verification pipeline
hardware/phase1-module/lib/PARTS-TO-DOWNLOAD.md	Exact orderables, package corrections, verified pricing

Repository layout

text

docs/                         Design docs 01..10, build guide 11, bench tests 12
  test-results/               Bench results (template + one file per board run)
hardware/common/              Shared generators, checkers, bom.py + lcsc_parts.py
hardware/phase1-module/       KiCad 7 project (schematics hand-owned; board generated + routed)
  tools/                      Generators + mechanical checkers (see README)
  lib/                        Vetted symbol + footprint libraries (shared by phase 2)
hardware/phase2-module/       KiCad 7 project — GENERATED (600 W module, docs/08)
hardware/phase3-backplane/    KiCad 7 project — GENERATED (8-slot backplane, docs/09)
hardware/phase3-manager/      KiCad 7 project — GENERATED (ESP32-S3 manager, docs/09)
firmware/
  common/labbench_can.h       CAN codec, shared module <-> manager
  module/core/                Portable control core (host-tested)
  module/                     STM32G431 bare-metal firmware (Makefile+arm-gcc)
  manager/core/               Portable manager core (host-tested)
  manager/idf/                ESP-IDF shell (needs IDF >= 5.1; unproven on silicon)
  tests/                      Host unit tests — `cd firmware/tests && make test`
  tools/lbcan.py              Bench helper: build cansend frames, decode candump

Status (2026-10-06)

Nothing has run on silicon yet; the first board to be built is the Phase-1 module. v0.1.0 was released from master on 2026-09-29.

Area	State
Design docs	Complete: 01–10, plus the build guide (11) and Phase-1 bench test procedure (12)
Phase-1 module (150 W)	100 × 80 mm, routed, 0 unconnected, 0 DRC errors, fab zip and CPL committed. OVP_TRIP routed to the MCU (PB4) for the firmware 0.2 OVP latch. L2 moved to a 5 × 5 mm land (2026-10-06). Next: order and run docs/12. The older 120 × 80 layout on branch `phase1-120x80` has wrong L1/U7 lands: do not order it
Phase-2 module (600 W)	130 × 90 mm, routed, 0 unconnected, 0 DRC errors, fab zip and CPL committed; pre-order review closed (HANDOVER); L2 moved to a 5 × 5 mm land (2026-10-06)
Phase-3 backplane	330 × 100 mm, fab-ready; gated on the XT60 polarity buzz-out (MECHANICAL.md)
Phase-3 manager	100 × 80 mm, routed, 0 unconnected, 0 DRC errors; L2 moved to a 5 × 5 mm land (2026-10-05)
Module firmware	v0.2 builds (~7 KB, bare-metal STM32G431) with the OCP backup and OVP latch; control core host-tested
Manager firmware	v0.2 builds on ESP-IDF 5.3.2; manager, SCPI and UI cores host-tested
BOM / sourcing	LCSC numbers in the schematics and per-board BOM and CPL files (`hardware/common/bom.py`); no `CHECK:` rows left (closed 2026-10-06); INA228 stock is thin (5 at LCSC); generic R/C parts not yet numbered
CI	GitHub Actions: host tests, module and manager firmware builds on every PR

Complete Phase-1 build (parts, five PCBs, stencil, shipping) ≈ US$100–125. HANDOVER.md has the detailed resume points. Work lands on the development branch through pull requests; master receives batched merges.

License

GPL-3.0 (see LICENSE).

Parts

Qty	Value	Footprint	References
6	M3	MountingHole:MountingHole_3.2mm_M3	H1, H2, H3, H4, H5, H6
3	Fiducial	Fiducial:Fiducial_1mm_Mask2mm	FID1, FID2, FID3
2	0m5 3920	labbench:R3920_BVS	RS1, RS2
2	100n	Capacitor_SMD:C_0603_1608Metric	C1, C3
1	120R slot0-end	Resistor_SMD:R_0603_1608Metric	R2
1	120R slot7-end	Resistor_SMD:R_0603_1608Metric	R3
1	1K	Resistor_SMD:R_0603_1608Metric	R1
1	470u/50V	Capacitor_SMD:CP_Elec_16x17.5	C2
1	E-STOP NC (jumper if absent)	Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical	J2
1	INA228	Package_SO:VSSOP-10_3x3mm_P0.5mm	U1
1	MANAGER	Connector_PinHeader_2.54mm:PinHeader_1x20_P2.54mm_Vertical	J1
1	RETURN LUG M6	MountingHole:MountingHole_6.4mm_M6_Pad_TopBottom	J31
1	SLOT0 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J20
1	SLOT0 XT60PW-F	labbench:XT60PW-F	J10
1	SLOT1 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J21
1	SLOT1 XT60PW-F	labbench:XT60PW-F	J11
1	SLOT2 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J22
1	SLOT2 XT60PW-F	labbench:XT60PW-F	J12
1	SLOT3 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J23
1	SLOT3 XT60PW-F	labbench:XT60PW-F	J13
1	SLOT4 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J24
1	SLOT4 XT60PW-F	labbench:XT60PW-F	J14
1	SLOT5 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J25
1	SLOT5 XT60PW-F	labbench:XT60PW-F	J15
1	SLOT6 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J26
1	SLOT6 XT60PW-F	labbench:XT60PW-F	J16
1	SLOT7 SIG	Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical	J27
1	SLOT7 XT60PW-F	labbench:XT60PW-F	J17
1	SMBJ33A	Diode_SMD:D_SMB	D5
1	VBUS+ LUG M6	MountingHole:MountingHole_6.4mm_M6_Pad_TopBottom	J30

Questions

How big is the Phase3-backplane PCB?

It measures 330 × 100 mm and has 2 copper layers, 1.6 mm thick.

What parts does the Phase3-backplane use?

39 parts, built around the SMBJ33A. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.

Where can I download the Phase3-backplane KiCad files?

From the udaravima/Lab_Bench repository on GitHub, at the commit this page was made from: the board is hardware/phase3-backplane/phase3-backplane.kicad_pcb and its schematic hardware/phase1-module/aux-rails.kicad_sch. PCBKit opens the board in the browser, with nothing to install.

Can I use the Phase3-backplane design in my own project?

Its repository publishes it under the GPL-3.0 licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).

Category and platform

Power

Project files

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A live frame, for any web page

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A picture

<img src="https://pcbkit.io/embed/boards/udaravima-lab-bench-phase3-backplane.jpg" alt="Phase3-backplane" width="1200" height="900">

A picture that opens the board, for a README

[![Phase3-backplane](https://pcbkit.io/embed/boards/udaravima-lab-bench-phase3-backplane.jpg?size=s)](https://pcbkit.io/boards/udaravima-lab-bench-phase3-backplane)

Source

Repository: udaravima/Lab_Bench
Board file: hardware/phase3-backplane/phase3-backplane.kicad_pcb
Commit: e5eb24f
Licence: GPL-3.0

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