Encoder

Main board

The Micras micromouse main board: a 50 x 90 mm, 4-layer, 1.04 mm board. It carries the STM32H725RGV6 controller, the battery input and power conversion, the two locomotion motor bridges and the fan driver, the IMU, four wall sensors, the slots for the two encoder boards, and the user interface.

The circuit replicates the MicrasMainBoard Altium design part for part: every part keeps its designator, and micras-pcb previous compare main checks the netlist against that design's connectivity (previous/board.json) plus the changes declared in changes.toml.

Files

The board files are in boards/main/ (this README sits in its layout/ folder); spec/ is at the repository root.

Each sheet's docstring describes its circuit with the datasheet figure, table or equation behind each value. Each module is its own sheet of the KiCad schematic (Project(..., layout=False) in its .zen), and the layout is the board's. A module's signal ports take the names of the nets they carry (Fan_Enable, not FAN_ENABLE), so the sheet pins match the root's labels; the SPI buses and the Motor_*_Sense+/- nets, whose names are not identifiers, keep their port names. The battery's minus, GND_BAT, is a ground port of REGULATORS: it appears on the root only at the sheet pin, and a power symbol there needs nothing else to join it.

Power

Power modes:

• Battery: SW4 turns Q6 on, which connects the pack minus to GND; the buck makes 3V3 and the boost makes +20V from VBAT.
• USB: VBUS feeds U3, which makes 3V3.
• Debugger: P1 pin 1 is on 3V3, so an SWD probe can power the logic.

In the USB and debugger modes 3V3 also reaches VBAT backwards through IC7, and from there the boost and the fan driver: the design review (hw_debug/schematic_review.md C3-C5) describes this and the bench measurements.

MCU supply

The VFQFPN68 STM32H725 has no VDDLDO pin: the core always runs from the on-chip SMPS, in the "Direct SMPS supply" of ST AN5419 Figure 5 (p10). VLXSMPS drives L1 (2.2 uH), whose output is VCORE; VFBSMPS and the three VCAP pins all sit on VCORE, with 2 x 10 uF at the inductor (C3, C4) and 100 nF at each VCAP pin (C7, C6, C5), as AN5419 Table 2 (p7-8) requires. The firmware selects PWR_DIRECT_SMPS_SUPPLY to match.

VBAT (pin 1), the backup-domain supply, is on 3V3 with C8 100 nF and C9 1 uF at the pin: with no backup battery, AN5419 Table 2 ties VBAT to VDD. The pin's range is 1.2-3.6 V (DS13311 Table 13 p116), absolute maximum 4.0 V (Table 10 p114).

Signals

Net names follow the firmware's pin map (Motor_Left_PWM_FW, Encoder_Left_CSn, Wall_Sensor_0, ...). Nets local to a sheet carry the sheet's prefix (REGULATORS.BOOST_FB). The IMU and both encoder boards share SPI_SCK/SPI_MISO/SPI_MOSI, each with its own chip select.

PA5, PC15, PH0 and PH1 are unused.

Board

4 copper layers, 1 oz outer and 0.5 oz inner copper, 0.2104 mm prepreg (Dk 4.4) and 0.5 mm core (Dk 4.48), from the Altium layer stack: 1.0212 mm of copper and dielectric. The KiCad stackup adds Zener's fixed 10 um solder mask a side, 1.0412 mm (spec/main.toml); Altium's 15.24 um resist makes the same stack 1.0517 mm. The board is ordered as JLCPCB's 1.0 mm 4-layer board. Design rules: 0.1 mm clearance, 0.254 mm default track, 0.45 / 0.3 mm vias (0.5 / 0.3 and 0.8 / 0.4 mm also used), 0.2 mm copper to edge, 0.02 mm solder mask expansion, all from the Altium design rules; rules/jlcpcb.kicad_dru adds JLCPCB's limits on top. The drill and placement origin of the fab outputs is the Altium origin, the rear edge centre at KiCad (148.501075, 150.00362).

Layout

The layout is the Altium MicrasMainBoard.PcbDoc's, in the same KiCad coordinates: MicrasHardware and the firmware place the board by them, with the wheel-axle midpoint (between the encoder slots) at KiCad (148.5011, 113.5036). previous/transfer_layout.py builds it from the KiCad conversion of that PCB and previous/rework.py adds the copper of the two declared changes; running the script again changes nothing.

Where things are, in the robot frame (x forward, y left, from the axle midpoint; spec/main.toml):

• Front (x 30-54 mm): IC1 at x = 37, the wall sensors W1-W4 at the front corners, the LEDs D1/D2/D4/D5 on the front edge, the buttons SW2/SW3/SW5.
• Middle (x -10 to 30 mm): the IMU IC2 on the axle midpoint, the encoder slots EC1/EC2 at y = -/+6.9, the wheel notches on both sides, the fan hole at x = 17.5 with the fan connector M3 and the buzzer BZ1 beside it, the 3V3 buck IC7/L3 and the USB LDO U3 front right, the DIP switch SW1 and the SWD header P1 at the sides.
• Rear (x below -5 mm): the current amplifiers IC3/IC4 and the shunts R31-R33 behind the axle, the fan driver IC6, the boost U1/L2, the bridge IC5 with the motor connectors M1/M2 at the rear corners, the battery connector J1 with the switch SW4/Q6 rear right, the USB-C receptacle U2 on the rear edge.
• Screw holes H1-H4 (2.4 mm, M2) at (2.5, +/-11.75) and (-15.5, +/-19.25).

Resistors, ceramic capacitors and the LEDs D4/D5 use KiCad's generic footprints, each centred on its pads' positions in the Altium footprint: the routing lands on the same pad centres, up to 0.12 mm from a pad's centre where the KiCad pad pitch differs (0805/1206 capacitors). The current-sense shunts R31-R33 keep the Altium land pattern and model (components/micras/R2512: 1.45 x 3.45 mm pads). D4 and D5 carry KiCad's LED model scaled to their datasheet heights, 0.80 mm (NCD0603Y2) and 0.60 mm (KT-0603R), so the 3D export has the fitted parts' height.

Zones, as previous/transfer_layout.py sets them from the Altium polygons and rules:

• The teardrops of the Altium design are plain copper zones (priorities 100 and up, above every pour): KiCad 10 does not save a teardrop zone's UUID and orders zones by UUID, so a board with teardrop zones changes on every save. They fill with a 0.1 mm minimum width, JLCPCB's minimum copper feature, which leaves out only their thinnest cusps.
• The pours drop copper narrower than 0.1 mm (the Altium polygons' neck width). In1.Cu and In2.Cu join through-hole pads with thermal reliefs, four 0.254 mm spokes across a 0.254 mm gap, and vias solidly; F.Cu and B.Cu join everything solidly (Altium rules PolygonConnect and PolygonConnect_Top/BottomLayer).
• In1.Cu and In2.Cu stay 1.559 mm and 2.074 mm from each screw hole's centre, as the Altium pours do: a copper-pour keepout per hole and layer.
• U2's peg-hole keepouts cover all four copper layers.

The Edge.Cuts outline is the Altium one without its six duplicated vertices (lines of 1-10 nm, which KiCad reads as a malformed outline); the lines next to them meet within 10 nm of where they did.

Copper of the two changes (KiCad coordinates, as in rework.py):

• VBAT pin on 3V3 (C1). IC1 pad 1 with C8 and C9 sits on a short top-layer cluster that reaches the In2.Cu 3V3 plane through the via at (155.105, 75.582); a 0.2 mm top-layer bridge joins pad 1 to pad 68 (VDD) across the package corner, 0.2 mm from pads 2 and 67.
• VCORE (C2). L1, C3 and C4 feed VFBSMPS (pad 7) on the top layer. A 0.5 mm In2.Cu route carries the core current from the via beside C3/C4 to the three VCAP pins: down to a via on the VCAP3 (pad 66, C5) track, under the package along y = 77.06 between the exposed pad's ground vias, with a branch to VCAP2's via pair (pad 49, C6), and 0.4 mm on the last 2.7 mm to a via on the VCAP1 (pad 33, C7) track. It runs as a tree, so the 3V3 plane flows around it. The VCAP3 via keeps 0.13 mm from the bottom-layer Encoder_Right_CSn track, the widest spot between the pad 66 and pad 68 tracks.

Differences from the Altium board

Apart from C1 and C2, the board's copper, mask, paste, drills and outline match the Altium MicrasMainBoard's own Gerbers (its CAMtastic output) except where KiCad, JLCPCB's rules or the generic parts set them otherwise:

Known faults

The board keeps its previous revision's circuit, so the design checks fail where that circuit is wrong. Each failing check, the fault behind it (with its item in the design review, hw_debug/schematic_review.md), the requirement it breaks, and the fix. Every fix listed keeps the board's functions.

The layout gates (layout-check runs the same KiCad DRC as drc; its netlist sync is clean) and the layout tests fail on these, every one from the previous layout, its conversion from Altium, the copper of change C2, or a footprint:

ERC passes with two warnings accepted in erc.toml, both from how pcb 0.4.81 labels a net that crosses a module sheet: a global label on the root and on the sheet, beside the sheet pin and the hierarchical label (diodeinc/pcb#1520). That gives 46 same_local_global_label, and 14 multiple_net_names where the port name is not the net's (the SPI bus members, MOTOR_L_SENSE_P for Motor_L_Sense+). On the root, the sheet symbols sit close enough for their pin labels to overlap the next sheet's box. The netlist is right (LVS and previous pass); the warnings go away with a pcb release that includes diodeinc/pcb#1522, which generates the sheet pins and hierarchical labels alone, and the [accepted_warning] table goes with them.

Requirements without a check, and why:

• VDDA through a ferrite (m9): AN5419 Table 2 allows it ("can be connected through a ferrite bead"), it does not require it.
• 1 uF + 100 nF at EC1/EC2 (m19): the AS5047U asks for 100 nF at the chip, which the encoder board has.
• Ceramics of several uF at the L6205 (M8): the L6205 datasheet asks for 100-200 nF near the pins plus bulk, which the board has; the ripple current depends on motor currents no document gives.
• Boost current limit against J1 (m3): no source bounds it; the 3 A JST PA rating is below the fan driver's own 5 A limit, so the bound is the battery harness, not the boost.
• L2 saturation against the boost current limit: the XAL6030-102 package does not know whether its 23 A is the saturation current (TODO in its docstring).
• L6981 slope compensation (Eq. 38): with Eq. 13 read literally, ST's own 22 uH evaluation set-up fails it too, so the reading is not reliable enough for a gate.
• Capacitor voltage derating: the ratings are checked against the worst-case net voltage (capacitor_voltage_ratings); no sourced derating factor is applied.

Open items

• Solder mask colour and surface finish: not recorded in the Altium design; the board uses the 4-layer defaults until they are confirmed.
• Check every part's placement rotation in JLCPCB's assembly preview, then set rotation_verified = true in parts/jlc.toml.
• Fix the known faults.