Wifi floppy

Rev C: on-board RP2350, schematic and routed board

Rev B with the PIM726 module replaced by its parts on our PCB: RP2350B, 16 MB flash, 16 MB PSRAM, RM2 radio, crystal, core regulator, USB-C, BOOTSEL, SWD. Every GPIO stays where the PIM726 has it, so the firmware's pin map and the pico-sdk board definition are unchanged. Same outline as rev B. Rev B's files are untouched.

The schematic and the routed board agree, and nothing else about the board differs from using a PIM726 on rev B. It is still not a board to order: see "Owed before a fab order".

Result (2026-11-05)

Parts

From Pimoroni's Pico Plus 2 W schematic unless noted.

Left out as nothing here uses them: the VSYS sense divider and its MOSFET, the 1k links from GP26-28 to GP40-42, the user switch, the Qw/ST connector (its GP4/GP5 are MTR and DIR here; operator confirmed 2026-11-05), the 40-pin header.

The reset button is out (operator, 2026-11-05: BOOTSEL is needed, PIM726's RESET is not). Test pad TP1 on RUN replaces it; RUN keeps its internal pull-up (RP2350 pin table), as on Pimoroni's sheet.

Scope (operator, 2026-11-05): everything stays as it is with a PIM726. So the J5 DRIVE passthrough, Amiga RESET line and keyed I2C connectors from the earlier rev C plan are not on this board. Firmware does not use what is left out: GP26-28, GP43 and GP45 appear in comments only.

Schematic

rev-c.kicad_sch is rev B's sheet with the module out. mcu.kicad_sch (RP2350B, supplies, crystal, RM2) and support.kicad_sch (USB-C, 3.3 V, flash, PSRAM, BOOTSEL, debug) hold the module's parts, after Pimoroni's sheets. rev-c-schematic.pdf is the print. All new symbols are in rev-c-lib.kicad_sym; apart from RM2 (drawn from RM2 table 2) and the PSRAM (KiCad's APS6404L with ISSI's value) they are KiCad's own.

The sheets are the source: edit them in KiCad. build_board.py reads their netlist for names, values, footprints and links, which is why parity is clean. Swapping MTR and DIR, or removing a PWR_FLAG and a no-connect, in a copy made verify_sch.py fail, as it should.

Differences from Pimoroni: NCP1117 with 10 uF either side (AP7366, 2.2 uF; the 2026-10-20 note's part), 16 MB PSRAM, 10 uF added at RM2's VDDBAT, BOOTSEL as 1k and switch without their diode and user-switch network. Pull-ups (flash CS 3k3, PSRAM CS 100k) and series resistors (27.4 ohm) are Pimoroni's.

RM2 antenna

The module sits in the bottom right corner with its antenna on the board edge. Of Raspberry Pi's 35.5 x 18.5 mm keep-out, only 26 x 5 mm is on the board; the rest is air. It is a rule area on all layers, about where rev B's was. In a case, what is beyond the edge also counts.

16 MB PSRAM: what is and is not known

From the ISSI datasheet and hardware_psram/psram.c: same pinout and commands as the APS6404 (35h, EBh with 6 wait cycles, 38h), 2.7-3.6 V, 1024-byte pages. The pico-sdk's size detection names ISSI's 16 MiB ID, and it breaks bursts at 1024 bytes, so a burst cannot cross the part's two stacked dies (its datasheet forbids that). None of it has run on hardware. Firmware needs PICO_PSRAM_SIZE_BYTES and SLOT_COUNT raised to use more than 8 MB.

Owed before a fab order

1. A person reading the schematic. Nobody has yet.
2. The core regulator and crystal by hand. Raspberry Pi say a regulator layout other than theirs is at your own risk. Here L1 and the capacitors are placed close but autorouted. Copy their layout.
3. A person reading the autorouted copper: QSPI lengths, the USB pair (12 Mbit/s, so no impedance control needed, but keep it short), the floppy lines. It has too many vias.
4. Footprints against samples: RM2, USB-C, buttons.
5. Board-edge clearances: SW1 moved in 0.3 mm, now about 0.55 mm. M1 at the edge is intended.
6. Sourcing: not checked. The JLC search was down; JLCONE not used.
7. Heat: 5 V to 3.3 V at Wi-Fi peaks is about 0.7 W in U5. Measure it.

Rebuild

In order, with KiCad's Python and Freerouting 2.5.0: variants.sh runs build_board.py (places), stitch.py (joins power pins to the planes), Freerouting on the outer layers, and route.py (adds the planes and pours), into v1/. Then by hand: clean.py v1/rev-c.kicad_pcb v1/drc1.json removes the router's stray vias and widens any neck below 0.09 mm, finish.py adds fiducials and sets the silkscreen, verify_pins.py checks. The fiducials landed at free spots, not in the corners: place them properly in KiCad. Part references on the new parts are hidden until someone places them.

package.sh builds rev-c-kicad-project.zip: the project with wifi-floppy-lib copied in and the library tables pointed at the copies, so it opens anywhere with KiCad 10. Rebuild it after any change.