Dogrudan sdr C

Direct-Sampling SDR

A direct-sampling software-defined radio transceiver and its power amplifier for the amateur bands from 1.8 MHz to 54 MHz.

What the equipment does

The receiver samples the antenna signal directly. It does not use a mixer and it does not use an intermediate frequency. Four receive channels operate at the same time. The four channels use one clock. Thus the channels keep a constant phase relation.

The transmitter uses the same four channels in the opposite direction. The power amplifier increases the transmit power to a maximum of 100 W.

The three boards

Board B does not exist. The first design had a separate clock board. The clock circuit is now on board A, because the distance from the clock to the ADC controls the phase accuracy.

Signal path

The receive path:

1. The antenna connects to board C.
2. The band filter removes the unwanted signals.
3. The transmit/receive relay connects the filter to the receive path.
4. The attenuator sets the signal level.
5. Board A receives the signal.
6. The transformer makes the signal differential.
7. The ADC samples the signal.
8. The FPGA processes the samples.
9. The ethernet interface sends the data to the host.

The transmit path:

1. The host sends the data to board A.
2. The DAC makes the analog signal.
3. Board D receives the signal.
4. The driver stage increases the power.
5. The four final transistors increase the power to 100 W.
6. The low-pass filter removes the harmonics.
7. The directional coupler measures the forward and the reflected power.
8. The antenna radiates the signal.

Why direct sampling

A superheterodyne receiver mixes the input signal to a lower frequency. The mixer makes unwanted products. The local oscillator adds noise. Each conversion stage adds distortion.

A direct-sampling receiver has none of these stages. The ADC samples the antenna signal. The remaining signal path is digital, thus it is exact and it does not change with the temperature.

The clock sets the limit at high frequency. The jitter of the clock gives this maximum signal-to-noise ratio:

SNR = -20 x log10(2 x pi x f x t_jitter)

The VCXO contributes 60 fs and the fan-out buffer adds 54 fs in a narrow band or 150 fs in a wide band. Together they give 81 fs and 162 fs.

In the amateur bands the noise of the ADC is the limit and the clock is not. The clock becomes the limit only when the receiver undersamples near 500 MHz. A better clock part costs ten times more, and 66 dB is still 11 effective bits.

Why four coherent channels

Four channels that share one clock keep a constant phase relation. This makes these functions possible:

• Removal of a local noise source with a second antenna
• Measurement of the direction of a signal
• Increase of the antenna gain in one direction
• Measurement of meteor trails with two or more sites

A receiver with one channel cannot do these functions.

Licenses

Repository content

The schematics are not drawn by hand. Python scripts make them. Each script writes one sheet. To change a sheet, change the script and run it again. The document docs/TOOLS.md gives the procedure.

Status

The three schematics are complete. The electrical rule check finds no errors on the three boards. The placement is complete. The routing is in progress. No board is ready for manufacture.

The gateware operates in simulation. 21 test benches pass. The design fits in the ECP5-25F and it meets the timing of all five clocks. The receive chain, the transmit chain, the packet interface and the control interface are complete. The SDRAM interface and the digital predistortion do not exist.

Verification tools examine the boards and the schematics. They find faults that the electrical rule check cannot find. An example: a symbol pin number that does not agree with a footprint pad number makes a net that goes nowhere, but the rule check sees a correct wire. The commit messages give the details of each fault.