Base64

Base64

A 68k carrier board in DIP-64 that takes the iCESugar-Pro-v1.3 FPGA module

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Contents

• Hardware overview (Rev C)
• Clock architecture
• Required module
• Bill of materials
• Build guide
• Status

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Hardware overview (Rev C)

• 4-layer PCB with continuous ground plane on layer 2 and +5V plane on layer 3
• iCESugar-Pro v1.3 FPGA module mounts via 200-pin SO-DIMM (DDR2) socket
• DIP-64 footprint, pin-compatible with the MC68000 socket in an Amiga 500 (or similar 68k host)
• 7× SN74CBTD3861 FET bus switches for bidirectional 5 V ↔ 3.3 V level translation on all bus signals
• Clock subsystem: 7 MHz host clock → 84 MHz phase-aligned output to the FPGA, locked to the host's 7 MHz with ~300 ps skew
• Autoconfig daisy-chain header (J2) — Amiga autoconfig is implemented and working; J2 must be jumpered or daisy-chained for the board to configure
• 3.3 V rail generated locally from the 5 V CPU socket supply via TLV75533 LDO

Clock architecture

The host system provides a 7.09 MHz reference (E-clock derivative) on the CPU socket pin 15. This is buffered by the 74LVC1G17 Schmitt-trigger gate (powered from the local 3.3 V rail, with 5 V-tolerant inputs) and routed both to the FPGA at PT27A (C7, PCLKT0_1/+) and to the ICS570B zero-delay clock multiplier (configured for 12× via floating S0/S1 with CLK/2 feedback).

The 570B produces a phase-aligned 84 MHz on CLK and 42 MHz on CLK/2. The 84 MHz output feeds the FPGA at PL26A (L1, PCLKT6_1/HS+), which is well above the ECP5's 8 MHz PFD minimum and locks reliably to the on-chip PLL. Inside the FPGA, the 84 MHz is divided down to produce turbo CPU clocks (14 / 21 / 28 / 42 MHz) that remain phase-aligned to the original 7 MHz reference.

Required module

The Base64 carrier board requires an iCESugar-Pro v1.3 FPGA module by Muse Lab, which mounts into the SO-DIMM socket (J1). The module carries the Lattice ECP5 LFE5U-25F-6BG256C FPGA along with onboard 32 MB SDRAM, 32 MB SPI flash, and an iCELink USB-C programmer.

Available from the official Muse Lab AliExpress store.

Bill of materials

Notes on selected parts

U11 (CPU socket pins): these are round male pins supplied as 40-pin breakaway pin strips on 2.54 mm pitch, with ~11.96 mm overall pin length (top of pin to bottom). Break each strip down to a 32-pin section — you need two such sections, so two strips minimum. See step 8 of the build guide for fitting them.

J2 (autoconfig header):

• Pin 1: /CFGOUT
• Pin 2: /CFGIN (with 10 kΩ pull-up via R5)
• Pin 3: GND

This header supports Amiga-style autoconfig daisy-chaining, and autoconfig is implemented and working in the current FPGA designs. J2 is therefore not optional — it has to be wired one of these two ways:

• No other autoconfig device on the side expansion (e.g. no A590): place a standard 2.54 mm jumper shunt across pin 2 (/CFGIN) and pin 3 (GND) so the Base64 autoconfigs immediately.
• A side expansion autoconfig device is present: connect that device's /CFGOUT to J2 pin 2 (/CFGIN) instead, so the devices daisy-chain in the expected order — side expansion configures first, then Base64.

If neither connection is made, R5 holds /CFGIN high, the board waits for its turn in the chain that never comes, and it will not appear to the system.

For use in non-Amiga 68k systems, J2 is not applicable in its standard form, though it could potentially be repurposed depending on the target system.

J2 uses a standard 0.64 mm square 2.54 mm pitch right-angle pin header. Available from AliExpress directly as a 3-pin part, or cut from a 40-pin breakaway strip.

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Build guide

This is how I build the board: everything hand-placed and hand-soldered, then a single pass through a desktop reflow oven to even out the joints, and finally the through-hole parts. It is not the only way to do it — see alternative approaches if you are building more than one or two boards — but it needs no stencil and no paste, and it gives a clean, repeatable result.

Everything below assumes leaded solder. If you use lead-free you will need a correspondingly hotter reflow profile.

Tools and consumables

1. Bus switches and their decoupling caps

Work in the order C2, U2, C3, U3, C4, U4 … C8, U8 — one capacitor, then the IC it decouples, then the next pair.

It is tempting to place all the capacitors in a single pass, but C2–C8 sit right next to the drag-solder path along U2–U8. With all of them already fitted, drag-soldering the TVSOP-24 packages becomes much more awkward. Alternating keeps the area around each IC clear when you need it.

2. Remaining passives and the small ICs

With the bus switches down, solder the resistors (R1–R5) and the remaining capacitors (C1, C9, C10, C11). Then fit the three remaining ICs: U9 (Schmitt buffer), U10 (LDO) and U1 (clock multiplier).

3. SO-DIMM socket (J1)

Once all other surface-mount parts are on, place the SO-DIMM socket. There is a little wiggle room in the footprint, so take the time to align and centre it as well as you can against the silkscreen before tacking it down. Tack one corner, re-check the alignment along the whole length, then tack the opposite corner.

4. The 200 signal pins

I solder these pin by pin rather than drag-soldering. The socket contacts are fine and springy, and a drag tip tends to bend and flex them, which makes bridges easy and a clean result hard.

Instead: use a 1 mm tip, flux the pins, pick up a small blob of solder on the tip and transfer it to a pin — or two pins at a time once you find a rhythm. It is tedious, there is no way around that. What matters is that every pin ends up with a small but definite amount of solder on it.

Don't worry if the row looks uneven at this stage. The reflow step later will sort it out.

Hand-soldering the 200 pins with 0.5 mm Sn60Pb40. Uneven at this point — that is expected.

5. Retention arms to the large GND pads

The socket's two metal retention arms land on large ground pours, which sink far more heat than a normal iron can deliver. I use the ZD-915 desoldering station for this because it has the thermal capacity; a large chisel tip on a high-power iron will also work.

1. Cover U8 and R5 with kapton tape first — they sit close to the pad and you do not want to disturb them.
2. Flux both pads.
3. Feed roughly a centimetre of 1 mm Sn60Pb40 into the ZD-915 nozzle and set the station to 360 °C.
4. Come in at an angle so the nozzle touches both the exposed part of the pad and the arm at the same time.
5. Hold with gentle pressure for 3–4 seconds until the solder flows down and spreads across the pad, then lift off.

Be careful not to let the nozzle rest against the connector body — the plastic will melt. As with the pins, the joint does not need to look pretty yet.

ZD-915 at 360 °C on the ground pad, with U8 and R5 masked off under kapton tape.

6. Reflow

At this point everything except the through-hole parts is soldered. Clean the spent flux off the board, apply a fresh coat, and run it through the oven.

I use a T-962 desktop IR oven with the Amtech SynTECH-LF profile, which ramps to a 240 °C peak and then cools down.

Two boards loaded in the T-962.

The Amtech SynTECH-LF profile as shown on the T-962.

Gravity and surface tension do the rest — joints that looked lumpy going in come out even.

7. Inspect and clean

Inspect every pin under magnification: each should have a clean fillet, and there should be no bridges anywhere along the socket.

Then clean the board with cotton buds and IPA.

For the ICs, don't use neat IPA — it lifts the laser marking off the packages. I use a general-purpose electronics cleaner instead, with the compound:

Hydrocarbons, C6-C7, n-alkanes, isoalkanes, cyclics, <5 % n-hexane, 2-Propanol

Applied to a clean cotton bud and wiped gently over the package, this cleans the ICs without erasing the text the way 100 % IPA does.

Electronics cleaner used on the ICs — cleans without taking the markings with it.

Two boards after reflow and cleanup.

8. Through-hole parts

Last come the two 32-pin strips (U11) and the 3-pin CFG header (J2). Fit J2 — it is required for the board to autoconfig, and you will need a jumper shunt for it unless you are daisy-chaining from another device. See notes on selected parts.

Push each 32-pin section through the carrier board pads from the underside and solder on the top side. The protruding bottom side is what plugs into the host system's MC68000 socket.

The 32-pin sections are broken out of cheap 40-pin breakaway strips, and the break leaves a rougher edge on that end. It makes no difference electrically, but it is a nice touch to orient both strips so the clean edges face the same way — which of course puts both rough edges on the other side.

Clean edges on the same side …

… and the two broken edges together on the other.

Finish with a final clean of the through-hole joints using cotton buds and IPA to remove the excess flux.

Alternative approaches

Hand-soldering the 200 pins is the slow way. Two alternatives worth considering:

• Solder paste and hot air on the SO-DIMM socket, with the connector's plastic body masked off with kapton tape so the hot air doesn't deform it.
• Order a solder paste stencil together with the PCBs. Then it becomes paste, place, reflow — and almost all of the hand work above disappears. Only worth it if you intend to build a batch.

A note on the FPGA module

On my own iCESugar-Pro module I found a mark on the 25 MHz crystal oscillator that looks like it may have been made by a pin during installation of the module. I can't say for certain where the dent came from, or whether it is a problem at all — it is worth a look under a microscope if you have one. As a precaution I put a piece of kapton tape over the oscillator.

Kapton tape over the 25 MHz oscillator on the iCESugar-Pro module.

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Status

Amiga autoconfig is implemented and working in the current FPGA designs — see the J2 notes for the jumpering it requires.

Rev C changes vs Rev B:

• ICS501MLFT clock multiplier replaced with ICS570BLFT (adds feedback pin for phase-aligned operation)
• 74AHCT1G17 (5 V) replaced with 74LVC1G17 (3.3 V, 5 V-tolerant inputs)
• Added TLV75533 LDO to generate local 3.3 V rail
• Clock subsystem reworked for cleaner signal integrity (source-side series termination on every branch)
• 84 MHz output routed to FPGA's PL26A (L1, PCLKT6_1/HS+) clock-capable input