MAIN LITE

IFS08-ES-MainLite

Hardware design, KiCad schematic and PCB layout of the MainLite, the minimal STM32H733ZG control module of the IFS08, developed for the ISC Formula Student Racing Team (Season 2025/2026). Mounted on a backplane, the same module becomes the AMS, the ECU or the uDV.

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Getting started

1. Create a GitHub account if you don't have one yet.

2. Download and install GitHub Desktop (beginner) or Git CLI (advanced).

   • If this is your first time using GitHub Desktop, make sure to read the User Manual.
   • If this is your first time using Git, start with a tutorial:
     • Git Tutorial
     • Atlassian Git Tutorial
   • Keep a copy of GitHub's Git Cheat Sheet handy as a reference.

3. Clone this repository to your machine:

   • SSH: git@github.com:isc-fs/IFS08-ES-MainLite.git
   • HTTPS: https://github.com/isc-fs/IFS08-ES-MainLite.git

4. Open IFS08-MainLite/MAIN_LITE.kicad_pro with KiCad 9.x.

How we work with this repository

Main branches

The repository follows standard ISC branching rules:

• main is the production branch. It contains only validated hardware releases, schematics, and documentation ready for track operations. Never work directly on it.
• dev (or active feature branches) is the development and integration point. Never commit directly to main — all changes arrive through a reviewed Pull Request.

main  ──────────────────●──────────────────────●──▶  (validated releases only)
                        ↑                      ↑
dev   ──────●───●───●───●───●───●───●───●───●──●──▶  (continuous integration)
            ↑   ↑       ↑   ↑   ↑       ↑   ↑
          feat/1 fix/1 feat/2 fix/2   feat/3 fix/3

Feature branches

All work — whether a new hardware revision, firmware update, or bug fix — is done on a feature branch created from dev (or main). When the work is ready, a Pull Request is opened, reviewed, merged, and the branch is deleted.

feat/<n>   →  new functionality / hardware addition (feat/1, feat/2, feat/3 ...)
fix/<n>    →  bug fix / schematic correction       (fix/1,  fix/2,  fix/3  ...)

Step-by-step workflow

1. Create the branch:

   git checkout dev
   git pull origin dev
   git checkout -b feat/your-feature-name

2. Work and commit:

   git add .
   git commit -m "feat(hw): add reverse polarity protection to 5V input"

3. Push and open Pull Request:

   git push origin feat/your-feature-name

   Open a PR against dev, verify 0 KiCad DRC/ERC errors, provide test evidence, and request review from the Electronics Subsystem Technical Director.

1. Project Overview & System Purpose

The MainLite is a small, self-contained STM32H733ZG module: MCU, 3.3 V regulation, three CAN transceivers, IMU, microSD, USB-C and SWD. Everything that changes between car subsystems lives on the backplane it plugs into through two 1×18 2.54 mm headers (J3 and J4):

Every MainLite carries the ISC CAN bootloader in flash sector 0.

                 +--------------------------------------------------------------+
   USB-C (J5) ---+  ESD (D3/D4)   +5V <- VBUS (D11)        SWD (J2: GND/CLK/DIO/VDD)
                 |                                                              |
   +5V (J4.17/18)+--> LD39200 (U1) --> VDD 3.3 V --> J4.15/16                   |
                 |                                                              |
                 |      +--------------------------------------------+         |
                 |      |        STM32H733ZGTx (U5, LQFP-144)         |         |
                 |      |  HSE 24 MHz (Y1)                            |         |
                 |      +--+---------+---------+---------+------+----+         |
                 |         |FDCAN1   |FDCAN2   |FDCAN3   |I2C2  |SDMMC1        |
                 |      TCAN330   TCAN330   TCAN330   BMI088  microSD (J1)      |
                 |       (U2)      (U3)      (U4)     (IC1)    4-bit, CD PE3    |
                 |      120R R1   120R R5   120R R9                             |
                 +--------+---------+---------+-----------------------------+---+
                          |         |         |                             |
                   J4.3/4 CAN1  J4.5/6 CAN2  J4.7/8 CAN3     J3: 13 GPIO, USART10, 1-Wire
                                                            J4: SPI1 + nRF24 CS/CE/IRQ

2. Hardware Architecture & Electrical Specifications

3. Backplane Connectors (J3 / J4)

Per-role use of these pins (which GPIO is which signal on the AMS, ECU or uDV backplane) is defined by each backplane design.

4. Machine-Readable Pin Model

model/mainlite.pins.yaml (JSON twin: mainlite.pins.json) lists all 144 pins of U5: net, alternate function, whether and where each one leaves the module on J3/J4, and what it connects to on the board. It also describes the CAN, SDMMC, I2C, HSE, VBAT, SWD and USB interfaces. tools/gen_pins.py generates it from the schematic; CI fails a PR whose committed model is stale or whose schematic has KiCad ERC errors. Each change that reaches main is published as a pin-model-vX.Y release, so other repos (e.g. the virtual HIL) can check their pin definitions against a pinned version.

python3 tools/gen_pins.py        # after any schematic change; commit model/

Format, versioning and how to consume it: docs/pin-model.md.

5. Formal Design Documents & Reports

6. Repository Structure

IFS08-ES-MainLite/
├── .github/workflows/                 # CI: pin-model check + ERC, model release on main
├── docs/                              # Documentation
│   ├── bom/
│   │   └── MAIN_LITE_v1-1_BOM.html    # Interactive BOM
│   ├── MAIN_LITE_schematic.pdf        # Schematic PDF export
│   ├── pin-model.md                   # Pin model format & usage
│   └── WORK_ORDER_MAIN_LITE.md        # Synchronized Markdown Work Order
├── IFS08-MainLite/                    # KiCad Project Files (KiCad 9.x)
│   ├── Libraries/                     # Local symbols & footprints (BMI088, LD39200, LSM115J, switch, ISC logo, MainLite module)
│   ├── production/                    # Fabrication outputs (Gerbers, BOM, CPL)
│   ├── fp-lib-table                   # Footprint Library Table
│   ├── sym-lib-table                  # Symbol Library Table
│   ├── MAIN_LITE.kicad_pro            # KiCad Project File
│   ├── MAIN_LITE.kicad_sch            # Schematic
│   └── MAIN_LITE.kicad_pcb            # PCB Layout
├── model/                             # GENERATED pin model (mainlite.pins.yaml / .json)
├── tests/                             # Pin model invariants (unittest)
├── tools/                             # gen_pins.py, kicad_export.sh, erc_summary.py, ST pin data
├── WO_ES-IFS08-MainLite.pdf           # Official Work Order (PDF)
├── WO_ES-IFS08-MainLite.docx          # Official Work Order (Word)
├── .gitignore                         # KiCad and OS Ignore Rules
└── README.md                          # Repository Documentation

Libraries/MAIN_LITE/ holds the MainLite module symbol and footprint that backplane designs place to mate with J3/J4.

7. Author & Team Credits

• Subsystem: Low Voltage & Electronics Subsystem (ES)
• Author & Technical Lead: Raúl Morán
• Team: ISC Formula Student Racing Team — Universidad Pontificia Comillas (ICAI)
• Season: 2025 / 2026

ISC Racing Team — IFS08 Electronics Subsystem