Z80 romless sbc

pcb-z80

pcb-z80 is a container-only, repeatable build of the four-layer Z80 ROMless SBC PCB engineering design. It regenerates the KiCad schematic, places the four-layer board, routes a fresh Specctra session, imports and fills the board, runs strict ERC/DRC and net-parity checks, measures timing-sensitive buses, and exports a fabrication package.

The design is derived from the deterministic generators in gloveboxes/Z80ROMlessSBC at the revision recorded in SOURCE.md. The board uses F.Cu, In2.Cu, and B.Cu for signals while In1.Cu remains a continuous GND reference plane. The self-contained image pins its Java base digest, Python packages, Freerouting checksum, and exact KiCad 10.0.6 packages. No host Java, Python packages, Freerouting, pcbnew, or kicad-cli are used. Apple Container is the only runtime entry point.

Build and run

cd /Users/dave/GitHub/pcb-z80
./scripts/container-run build
./scripts/container-run info
./scripts/container-run all

Generated design and manufacturing artifacts are written under hardware/kicad/; tool provenance is recorded in build/toolchain.txt. Close the schematic editor, PCB editor, and KiCad project manager before running all, and keep them closed until it finishes. Builds refuse existing KiCad .lck files (including PCB locks) and never remove them.

all snapshots the generators and source/ inputs into a private staging workspace beside hardware/kicad/. Generation, routing, checks, and every fabrication/export step must succeed before the accepted output directory is replaced using same-filesystem renames. A failed build or interrupted promotion restores the previous directory; existing PCB, routing sessions, exports, and fabrication files are not deleted up front. Source inputs are never modified, and existing .kicad_prl local preferences are preserved on success. The generated .kicad_pro rules still come from source/, not local project edits.

If rollback cannot complete, the script reports the retained hardware/.kicad-build-*/ workspace; its accepted-kicad/ directory contains the previous accepted outputs. Do not start another build until that directory has been recovered. Uncatchable termination (for example SIGKILL or a host shutdown) can also leave this workspace: inspect it before rebuilding. info only updates tool provenance in build/ and container configuration; it does not create, remove, or modify files under hardware/kicad/. Unknown modes and extra arguments fail without running the pipeline.

The generated silkscreen labels J1's +5V/GND rails and retains the positive marks and negative-side shading on C9-C12. Do not remove polarity information to resolve drawing collisions. The board-only 3D render cannot establish socket-body clearance when component and socket models are absent; the 5.76 mm U1/U4 pin-row spacing is not the gap between purchased socket bodies.

Fit R23-R26 as 4.7 kOhm (5% or better), not 10 kOhm: the supported ATF22V10B's internal input pull-ups require stronger startup pull-downs. Apply external +5 V before connecting USB and disconnect USB before removing external +5 V. USB-only operation/programming of the populated board is unsupported because U9's AHCT245 data ports lack power-off isolation. Unexpected external-supply loss with USB connected requires additional hardware protection, not merely an inactive output enable.

Ubuntu dependency/security updates can change lower-level image contents, so the image is controlled and fail-closed but not claimed to be byte-identical across rebuild dates.

The routed board to open in KiCad is:

hardware/kicad/z80_romless_sbc.kicad_pcb

It is the only .kicad_pcb retained by a successful build. The temporary unrouted placement used to export the Specctra DSN is deleted immediately.

Completion criteria

• 79 electrical nets and 341 component endpoints match the independent manifest.
• Schematic ERC and PCB DRC complete with zero violations.
• Every selected address, data, clock, WAIT, and SRAM-control endpoint pair is routed.
• In1.Cu contains no signal tracks; PICO_CLK is via-free on F.Cu and D4 is via-free on In2.Cu.
• Gerbers, plated/non-plated drills, BOM, placement CSV, IPC-D-356, schematic exports, PCB drawings, and a 3D render are produced.

DRC completion is an electrical/manufacturing check, not physical hardware qualification. Initial bring-up still starts at a 1 MHz Z80 clock and proceeds through measured steps before claiming the design's at-least-8-MHz target.