Banyu done1 pcb

Banyu 40 kHz piezo receiver — wired schematic, Rev A-W

Updated drawing: signal paths, calibration path, filter networks, amplifier feedback and ADC host lines now use normal wires. Shared labels are limited to 3V3, GND and HREF supply connections. Internal signal labels occur once per net as annotations; they do not replace wiring. Values and electrical pin connections were preserved and checked against the original netlist manifest.

The Banyu_40k_Wired_Schematic.zip package is schematic-only. No PCB is needed to open it. The old unrouted PCB remains in the workspace as an earlier artifact; the PCB discussion below refers to that earlier version.

Open Banyu_40k_AFE.kicad_pro in KiCad, then open the schematic. The PDF is a read-only preview. Local symbol and footprint libraries are included. Equal net labels are electrically connected even where no long wire is drawn.

Status: editable, electrically connected engineering schematic; assigned footprints; PCB starting layout with nets/ratsnest, unrouted and not ready for manufacture. The board's grid placement is for inventory and connectivity, not an analog layout. No Gerbers are supplied. Routing, placement optimization, input protection, stability, ADC settling and hardware measurements are still required.

Checked with KiCad 9.0.6: schematic ERC 0 errors / 0 warnings; PCB/schematic parity 0 issues. Starter-board DRC has 97 unconnected items and no other violations. The default copper clearance is 0.15 mm to accommodate the MSOP-10 footprint; verify the intended fabricator's capabilities before routing.

This is one receiver channel based on ADI CN0350, adapted for a 40 kHz signal. Build three copies for the original TDOA array, or one per receiver for larger arrays. It interfaces to a floating raw piezo element, not an SR04T module's digital ECHO pin.

What changed from CN0350

R1 and C1 are provisional because actual piezo/cable impedance and received charge have not been measured. R1 was reduced from 1 kohm to 100 ohm to reduce the input RC effect at 40 kHz. R2=10 Mohm provides a 15.9 Hz feedback corner and a 10 ms discharge time constant; large transients can still cause long overload recovery. The new filters attenuate low-frequency disturbances only after the charge stage.

The filter sections each have K=1+5.90k/10k=1.59 and Q=1/(3-K)=0.7092. With equal R and C, f0=1/(2piR*C). All filter reference returns go to HREF, not ground, to preserve the 1.25 V operating point.

The combined -3 dB passband is approximately 22.9–57.9 kHz, relative to its 36.4 kHz peak, for the illustrative 2 nF sensor model. The 40 kHz signal is near the peak. This is a broad receive filter, not a 35–45 kHz brick-wall filter. The corners of cascaded sections do not equal the overall -3 dB edges. See frequency_response.svg, frequency_response.csv, and VALIDATION.md.

At 40 kHz, Cf=1 nF, Cp=2 nF and no gain shunt, the ideal calculated sensitivity is 1.729 mV/pC. Highest gain gives approximately 17.45 mV/pC. The corresponding ADC-only charge limits for +/-1.15 V headroom are about 665 pC and 66 pC. Earlier stages can overload first; these are not guaranteed sensor input ratings. Use the same gain selection on all TDOA receiver channels.

Connectors

J4 is a custom 8-pin header, not the original PMOD pinout. J3 is a single row of six pins: install at most one shunt, with power removed. Connecting multiple shunts puts gain resistors in parallel and increases gain. The piezo must be floating; a sensor with its negative lead tied to a grounded metal housing is not compatible with this input connection without redesign. The circuit is receive-only and does not include a transmit/receive switch or qualified ESD/transient protection. Do not connect a driven transmitter.

Sampling several receivers

Each module has its own AD7091R. Share ground, a suitable 3.3 V supply, hardware-generated CONVST_N and SCLK. A common CS_N can frame parallel reads, with one SDO input per ADC. Do not wire several SDO outputs together while their CS_N inputs are active. A single conventional MCU SPI input cannot capture three parallel outputs by itself; select an FPGA, parallel capture peripheral, or enough SPI peripherals with verified timing.

Sample at 500 kSPS or 1 MSPS per receiver. Follow the AD7091R timing diagram, including conversion, readout, acquisition and quiet times; 1 MSPS operation requires a suitable high-speed readout arrangement (datasheet example: 50 MHz SCLK). Sharing a trigger does not remove analog delay mismatch or ADC aperture skew. Measure those with a common input and calibrate the relative channel delay. Do not connect the modules' buffered HREF or VREF outputs together.

Bring-up and layout

1. Optimize the PCB placement before routing. Put the piezo input and U1A feedback parts together; keep SUM and both C1 connections very short. Separate SCLK/CONVST/SDO from the piezo and filter input nodes.
2. Use a ground plane with short return paths, local bypass capacitors at each supply pin, C8 at REF and C9 at REGCAP. Guard the sensitive SUM area at HREF without adding excessive capacitive loading. Clean flux and assess leakage.
3. Route filter feedback components close to the corresponding U1 pins. Match channel layout and components. Preserve R16 between U1D and C7/ADC VIN. The board presently has no tracks or planes, so it cannot be built as supplied.
4. Inspect and run PCB DRC after routing. Verify datasheet package orientation, connector numbering, pin maps, sensor isolation and protection requirements.
5. Apply a current-limited 3.3 V supply. Let REF settle (datasheet typical startup is 50 ms; verify on the actual board). Check VREF=2.5 V and HREF=1.25 V. All U1 outputs should sit near HREF with no signal.
6. Start with J3 open. At J2 apply a small 40 kHz sine, e.g. 10 mV peak with zero DC offset. C2=100 pF ideally injects 1 pC peak; exact injection depends on summing-node loop gain. This injection bypasses R1 and the sensor, so it validates the electronics but not underwater sensitivity or input loading.
7. Measure CHARGE, HP_OUT, LP_OUT, GAIN_OUT and ADC_IN. Sweep frequency, inspect ringing/oscillation, and verify 0.1–2.4 V ADC input headroom at maximum signal. Confirm ADC settling with actual conversion pulses, not just a sine-wave plot.
8. Repeat on all receivers using a common stimulus; characterize relative phase and burst delay. Then test real pingers and reflections at known positions.

Simulation and validation limits

validate_design.py checks the KiCad-exported netlist against the design manifest and all PCB pad nets. It solves the actual resistor/capacitor/op-amp network using modified nodal analysis and cross-checks the filter transfer against independent Sallen-Key equations. It includes a 300-draw component-tolerance calculation. The illustrative finite-op-amp model assumes a single dominant pole and 10 MHz unity-gain bandwidth. It is not a manufacturer macromodel or proof of stability.

ideal_ac_bench.cir is a portable SPICE AC starting point (x1 gain). It has ideal high-gain controlled sources, a 2 nF placeholder sensor, and no physical ADC, noise, bias, rail, or slew model. Its 1 A AC current excitation must be normalized as described in the file to obtain V/pC. It has been generated but not executed in SPICE. Import the vendor AD8608 model and measured sensor impedance for a more realistic transient and loop-stability study.

KiCad ERC does not validate analog performance. The inherited RC before the ADC is not by itself sufficient anti-alias filtering. Evaluate combined stopband attenuation against measured interferers at the selected sampling rate. No claim of measured underwater performance or fabrication readiness is made.

Relation to the MATLAB lab

This hardware has a 2.5 V ADC reference and 1.25 V bias; the existing lab defaults are 3.3 V and 1.65 V. For captured data use 12 bits, actual sample rate, Vref=2.5 V and bias=1.25 V (prefer calibrated measured values). Approximate conversion is centeredVolts = double(code)*2.5/4096 - 1.25, with calibration as needed.

Do not interpret the lab's assumed V/acoustic-unit sensitivity as pC/Pa. The new charge front end needs a measured charge sensitivity or impedance model. The lab has not been altered to pretend that its generic Butterworth filter matches this Sallen-Key circuit. Frequency-dependent phase and gain must be imported or modeled explicitly before comparing hardware with simulation.

Rebuilding

The checked-in KiCad files can be edited directly. Do not rerun the generator over manual edits: it recreates the schematic, project and PCB.

On the development machine:

& E:\kicad\bin\python.exe .\draw_wired.py
& E:\kicad\bin\kicad-cli.exe sch erc --exit-code-violations -o ERC.rpt Banyu_40k_AFE.kicad_sch
& E:\kicad\bin\kicad-cli.exe sch export netlist --format kicadxml -o connectivity.xml Banyu_40k_AFE.kicad_sch
& E:\kicad\bin\python.exe .\validate_design.py
& E:\kicad\bin\kicad-cli.exe sch export pdf -o Banyu_40k_AFE.pdf Banyu_40k_AFE.kicad_sch

Python needs numpy and KiCad's pcbnew module. Change the footprint-library path in the generator if KiCad is installed elsewhere. Run KiCad exports sequentially because CLI commands may update project settings.

Sources

• Analog Devices, CN0350: charge front end, reference arrangement and ADC interface inspiration. This adaptation is not ADI-tested.
• Analog Devices, AD8605/AD8606/AD8608 Rev O: pin maps, operating limits and amplifier specifications.
• Analog Devices, AD7091R Rev B: MSOP pin map, reference bypassing and conversion timing.
• Texas Instruments, Analysis of the Sallen-Key Architecture, SLOA024B: filter topology and transfer functions.
• Bundled standard footprints are from the installed KiCad 9 footprint library; see FOOTPRINT_LICENSE.md.