4 layers31.6 × 26.6 mm
Overview
The TCAN332GD is a CAN Transceiver made by Texas Instruments in a SOIC-8 package with 8 pins. -40℃~+125℃ 3V~3.6V 5Mbps CAN Transceiver SOIC-8 CAN Transceivers ROHS.
PCBKit's library has its KiCad symbol (Interface_CAN_LIN:TCAN332, from KiCad's library) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. JLCPCB lists it (part C1545625). 12 open-source boards in 12 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
14- Supply, least
- 3 V · VCC, recommended operating min · p. 5
- Supply, most
- 3.6 V · VCC, recommended operating max · p. 5
- Supply, absolute maximum
- 5 V · VCC, absolute max · p. 5
- Works from
- -40 °C · Operational free-air temperature min · p. 5
- Works up to
- 125 °C · Operational free-air temperature max · p. 5
- Junction, hottest
- 150 °C · Operating junction temperature max · p. 5
- Takes working
- 55 mA · VCC, normal mode dominant, typical bus load, max · p. 6
- Takes at most
- 60 mA · VCC, normal mode dominant, high bus load, max · p. 6
- A pin gives at most
- 8 mA · Logic output current absolute max · p. 5
- Junction to air (D (SOIC))
- 114.4 K/W · Junction-to-ambient thermal resistance · p. 5
- Junction to case (D (SOIC))
- 58.7 K/W · Junction-to-case (top) thermal resistance · p. 5
- Junction to board (D (SOIC))
- 55.2 K/W · Junction-to-board thermal resistance · p. 5
- Data rate, most
- 5 Mbit/s · TCAN33xG data rate max · p. 1
- Edge
- 6 ns · RXD output fall time typical · p. 8
What it is and has
9- Supply
- 3.3 V single supply · p. 1
- Data rate
- Up to 5 Mbps · p. 1
- Package options
- SOIC-8 and SOT-23 · p. 1
- Operating mode
- Normal mode · p. 1
- Bus pin fault protection
- ±14 V · p. 1
- Protection
- TXD dominant timeout · p. 1
- Protection
- RXD dominant timeout · p. 1
- Protection
- VCC undervoltage protection · p. 1
- Protection
- Bus pin current limiting · p. 1
Specifications
79| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply Voltage range VCC | min -0.3 · max 5 V | 5 | |
| Voltage at any bus terminal (CANH or CANL) V(BUS) | min -14 · max 14 V | 5 | |
| Logic input terminal voltage range V(Logic_Input) | min -0.3 · max 5 V | 5 | |
| Logic output terminal voltage range V(Logic_Output) | min -0.3 · max 5 V | 5 | |
| Logic output current IO(LOGIC) | max 8 mA | 5 | |
| Operating junction temperature range TJ | min -40 · max 150 °C | 5 | |
| Storage temperature Tstg | max 150 °C | 5 | |
| Electrostatic discharge V(ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; all pins except CANH and CANL; ±4000 V | min -4000 · max 4000 V | 5 |
| Electrostatic discharge V(ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; pins CANH and CANL; ±25000 V | min -25000 · max 25000 V | 5 |
| Electrostatic discharge V(ESD) | Charged-device model (CDM), per JEDEC specification JESD22-C101; all pins; ±1500 V | min -1500 · max 1500 V | 5 |
| Electrostatic discharge V(ESD) | IEC 61400-4-2 Contact Discharge; CANH and CANL terminals to GND; ±12000 V | min -12000 · max 12000 V | 5 |
| Supply voltage VCC | min 3 · max 3.6 V | 5 | |
| Logic terminal HIGH level output current IOH(LOGIC) | min -2 mA | 5 | |
| Logic terminal LOW level output current IOL(LOGIC) | max 2 mA | 5 | |
| Operational free-air temperature TA | min -40 · max 125 °C | 5 | |
| Junction-to-ambient thermal resistance RθJA | TCAN33x D (SOIC), 8 PINS | typ 114.4 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | TCAN33x D (SOIC), 8 PINS | typ 58.7 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | TCAN33x D (SOIC), 8 PINS | typ 55.2 °C/W | 5 |
| Junction-to-top characterization parameter ψJT | TCAN33x D (SOIC), 8 PINS | typ 11.7 °C/W | 5 |
| Junction-to-board characterization parameter ψJB | TCAN33x D (SOIC), 8 PINS | typ 54.6 °C/W | 5 |
| Average power dissipation PD | TCAN33x D (SOIC); VCC = 3.3 V, TJ = 27°C, RL = 60 Ω, SHDN, S and STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL(RXD) = 15 pF | typ 65 mW | 5 |
| Thermal shutdown temperature TSD | TCAN33x D (SOIC) | typ 175 °C | 5 |
| Thermal shutdown hysteresis THYS | TCAN33x D (SOIC) | typ 5 °C | 5 |
| Supply current Normal Mode ICC | Dominant; See Figure 18. TXD = 0 V, RL = 60 Ω, CL = open, S, STB and SHDN = 0 V. Typical Bus Load. | max 55 mA | 6 |
| Supply current Normal Mode ICC | Dominant; See Figure 18. TXD = 0 V, RL = 50 Ω, CL = open, S, STB and SHDN = 0 V. High Bus Load. | max 60 mA | 6 |
| Supply current Normal Mode ICC | Dominant with bus fault; See Figure 18. TXD = 0 V, S, STB and SHDN = 0 V, CANH = -12 V, RL = open, CL = open | max 180 mA | 6 |
| Supply current Normal Mode ICC | Recessive; See Figure 18. TXD = VCC, RL = 50 Ω, CL = open, S, STB and SHDN = 0 V | max 3.5 mA | 6 |
| Rising under voltage detection on VCC for protected mode UV(VCC) | typ 2.2 · max 2.6 V | 6 | |
| Falling under voltage detection on VCC for protected mode UV(VCC) | min 1.65 · typ 2 · max 2.5 V | 6 | |
| Hysteresis voltage on UV(VCC) VHYS(UVVCC) | typ 200 mV | 6 | |
| Bus output voltage (dominant) VO(D) | CANH; See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open; maximum = VCC | min 2.45 V | 6 |
| Bus output voltage (dominant) VO(D) | CANL; See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open | min 0.5 · max 1.25 V | 6 |
| Bus output voltage (recessive) VO(R) | See Figure 31 and Figure 19, TXD = VCC, STB, SHDN = 0 V, S = 0 V or VCC, RL = open (no load) | typ 1.85 V | 6 |
| Differential output voltage (dominant) VOD(D) | See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open | min 1.6 · max 3 V | 6 |
| Differential output voltage (dominant) VOD(D) | See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, 45 Ω ≤ RL < 50 Ω, CL = open | min 1.5 · max 3 V | 6 |
| Differential output voltage (recessive) VOD(R) | See Figure 31 and Figure 19, TXD = VCC, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open | min -120 · max 12 mV | 6 |
| Differential output voltage (recessive) VOD(R) | TA < 85°C, See Figure 31 and Figure 19, TXD = VCC, S, STB and SHDN = 0 V, RL = open (no load), CL = open | min -50 · max 50 mV | 6 |
| Differential output voltage (recessive) VOD(R) | See Figure 31 and Figure 19, TXD = VCC, S, STB and SHDN = 0 V, RL = open (no load), CL = open | min -50 · max 100 mV | 6 |
| Output symmetry (dominant and recessive) (CANHREC + CANLREC – CANHDOM – CANLDOM) V(SYM) | See Figure 31 and Figure 19, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open | min -400 · max 400 mV | 6 |
| Short-circuit steady-state output current, Dominant IOS(DOM) | See Figure 26, V(CANH) = –12 V, CANL = open, TXD = 0 V | min -200 mA | 6 |
| Short-circuit steady-state output current, Dominant IOS(DOM) | See Figure 26, V(CANL) = 12 V, CANH = open, TXD = 0 V | max 200 mA | 6 |
| Short-circuit steady-state output current, Recessive IOS(REC) | See Figure 26, –12 V ≤ VBUS ≤ 12 V, VBUS = CANH = CANL, TXD = VCC | min -5 · max 5 mA | 6 |
| Input threshold voltage, normal modes and selective wake modes VIT | See Figure 20 and Table 7; normal mode | min 500 · max 900 mV | 7 |
| Hysteresis voltage for input threshold, normal modes and selective wake modes VHYS | See Figure 20 and Table 7; normal mode | typ 120 mV | 7 |
| Common Mode Range: normal and silent modes VCM | Normal mode | min -12 · max 12 V | 7 |
| Power-off (unpowered) bus input leakage current IIOFF(LKG) | CANH = CANL = 3.3 V, VCC to GND via 0-Ω and 47-kΩ resistor | max 12 uA | 7 |
| Input capacitance to ground (CANH or CANL) CI | max 20 pF | 7 | |
| Differential input capacitance CID | max 10 pF | 7 | |
| Differential input resistance RID | TXD = VCC, Normal Mode | min 30 · max 80 kΩ | 7 |
| Input resistance (CANH or CANL) RIN | TXD = VCC, Normal mode | min 15 · max 40 kΩ | 7 |
| Input resistance matching: [1 – (RIN(CANH) / RIN(CANL))] × 100 % RIN(M) | V(CANH) = V(CANL) | min -3 · max 3 % | 7 |
| HIGH level input voltage VIH | TXD Terminal (CAN Transmit Data Input) | min 2 V | 7 |
| LOW level input voltage VIL | TXD Terminal (CAN Transmit Data Input) | max 0.8 V | 7 |
| HIGH level input leakage current IIH | TXD = VCC = 3.6 V | min -2.5 · typ 0 · max 3 uA | 7 |
| LOW level input leakage current IIL | TXD = 0 V, VCC = 3.6 V | min -4 · typ 0 · max 0 uA | 7 |
| Unpowered leakage current ILKG(OFF) | TXD = 3.6 V, VCC = 0 V | min -2 · typ 0 · max 2.5 uA | 7 |
| Input Capacitance I(CAP) | TXD Terminal (CAN Transmit Data Input) | typ 2.5 pF | 7 |
| LOW level output voltage VOL | RXD Terminal; See Figure 20, IO = 2 mA | typ 0.2 · max 0.4 V | 7 |
| Unpowered leakage current ILKG(OFF) | RXD = 3.6 V, VCC = 0 V | min -1 · typ 0 · max 1 uA | 7 |
| Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant and dominant to recessive tPROP(LOOP) | See Figure 23, S, STB and SHDN = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF | typ 100 · max 135 ns | 8 |
| Total Loop delay in highly loaded network tPROP(LOOP) | See Figure 23, S, STB and SHDN = 0 V, RL = 120 Ω, CL = 200 pF, CL(RXD) = 15 pF | typ 120 · max 180 ns | 8 |
| 2 Mbps transmitted recessive bit width tBUS_SYM_2 | See Figure 24, S or STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, tBIT = 500 ns | min 435 · max 530 ns | 8 |
| 2 Mbps received recessive bit width tREC_SYM_2 | See Figure 24, S or STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, tBIT = 500 ns | min 400 · max 550 ns | 8 |
| 2 Mbps receiver timing symmetry (tREC_SYM_2 - tBUS_SYM_2) ΔtSYM_2 | TCAN332G | min -65 · max 40 ns | 8 |
| 5 Mbps transmitted recessive bit width tBUS_SYM_5 | See Figure 24, S or STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, tBIT = 200 ns | min 155 · max 210 ns | 8 |
| 5 Mbps received recessive bit width tREC_SYM_5 | See Figure 24, S or STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF, tBIT = 200 ns | min 120 · max 220 ns | 8 |
| 5 Mbps receiver timing symmetry (tREC_SYM_5 - tBUS_SYM_5) ΔtSYM_5 | TCAN332G | min -45 · max 15 ns | 8 |
| Re-enable time after UV event tUV_RE-ENABLE | Time for device to return to normal operation from UV(VCC) under voltage event | max 1000 us | 8 |
| Propagation delay time, HIGH TXD to Driver Recessive tpHR | See Figure 19, S, STB and SHDN = 0 V. RL = 60 Ω, CL = 100 pF | typ 25 ns | 8 |
| Propagation delay time, LOW TXD to Driver Dominant tpLD | See Figure 19, S, STB and SHDN = 0 V. RL = 60 Ω, CL = 100 pF | typ 20 ns | 8 |
| Pulse skew (|tpHR - tpLD|) tsk(p) | See Figure 19, S, STB and SHDN = 0 V. RL = 60 Ω, CL = 100 pF | typ 5 ns | 8 |
| Differential output signal rise time tr | See Figure 19, S, STB and SHDN = 0 V. RL = 60 Ω, CL = 100 pF | typ 17 ns | 8 |
| Differential output signal fall time tf | See Figure 19, S, STB and SHDN = 0 V. RL = 60 Ω, CL = 100 pF | typ 9 ns | 8 |
| Driver dominant time out tTXD_DTO | See Figure 25, RL = 60 Ω, CL = 100 pF | min 1.2 · typ 2.6 · max 3.8 ms | 8 |
| Propagation delay time, bus recessive input to high RXD output tpRH | See Figure 20, CL(RXD) = 15 pF CANL = 1.5 V, CANH = 3.5 V | typ 62 ns | 8 |
| Propagation delay time, bus dominant input to RXD low output tpDL | See Figure 20, CL(RXD) = 15 pF CANL = 1.5 V, CANH = 3.5 V | typ 56 ns | 8 |
| Output signal rise time (RXD) tr | See Figure 20, CL(RXD) = 15 pF CANL = 1.5 V, CANH = 3.5 V | typ 7 ns | 8 |
| Output signal fall time (RXD) tf | See Figure 20, CL(RXD) = 15 pF CANL = 1.5 V, CANH = 3.5 V | typ 6 ns | 8 |
| Receiver dominant time out tRXD_DTO | See Figure 27, CL(RXD) = 15 pF | min 1.6 · typ 3 · max 5 ms | 8 |
Pins, by the datasheet
8- 1 TXD
- CAN transmit data input, LOW for dominant and HIGH for recessive bus states; integrated pull up. · p. 4
- 2 GND
- Ground connection. · p. 4
- 3 VCC
- 3.3-V supply voltage. · p. 4
- 4 RXD
- CAN receive data output, LOW for dominant and HIGH for recessive bus states; tri-state. · p. 4
- 5 NC
- No Connect – Not internally connected. · p. 4
- 6 CANL
- Low level CAN bus line. · p. 4
- 7 CANH
- High level CAN bus line. · p. 4
- 8 NC
- No Connect – Not internally connected. · p. 4
Parameters
16- Current - Supply
- 55mA
- Current - Supply(Max)
- 60mA
- Data Rate
- 5Mbps
- Features
- TXD dominant timeout, ESD Protection, Undervoltage Protection, Thermal shutdown protection
- Junction Temperature(Max)
- 150℃
- Number of Channels
- 1
- Operating Temperature
- -40℃~+125℃
- Output Current per Pin(Max)
- 8mA
- Quiescent Supply Current
- 20uA
- Rise Time
- 6ns
- Thermal Resistance(Junction to Ambient)
- 114.4℃/W
- Thermal Resistance(Junction to Board)
- 55.2℃/W
- Thermal Resistance(Junction to Case)
- 58.7℃/W
- Type
- CAN FD Transceiver
- Voltage - Supply
- 3V~3.6V
- Voltage - Supply(Absolute Max)
- 5V
Order codes
2- TCAN332GDLCSC C1545625
- TCAN332GDRLCSC C191010
Pinout
8| Pin | Name | Type |
|---|---|---|
| 1 | TXD | Input |
| 2 | GND | Power in |
| 3 | VCC | Power in |
| 4 | RXD | Tri-state |
| 5 | NC | Not connected |
| 6 | CANL | Input/output |
| 7 | CANH | Input/output |
| 8 | NC | Not connected |
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Is there a KiCad symbol and footprint for the TCAN332GD?
Yes. The symbol is Interface_CAN_LIN:TCAN332 and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the TCAN332GD?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the TCAN332GD datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the TCAN332GD?
JLCPCB lists it as part C1545625, with 0 in stock; the sellers' links on this page open their listings.
What can replace the TCAN332GD?
Parts like it in the library: the TJA1051T/3/1J by NXP Semiconductors, the SN65HVD230D by Texas Instruments, the TJA1042T/1J by NXP Semiconductors and the CA-IF1051S by Chipanalog. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the TCAN332GD?
12 boards in 12 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
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