2 layers99.6 × 100 mm
ISO6721BD
Texas InstrumentsExtended
-40℃~+125℃ 1 1 11ns 150kV/us 3000 50Mbps High Level SOIC-8 Digital Isolators ROHS
- Part id
- ti/ISO6721BD
- Category
- Digital Isolators
- Package
- SOIC-8
- Pins
- 8
- In stock
- 7,076 at JLCPCB (C5216430)
- Used on
- 3 open-source boards
Overview
The ISO6721BD is a digital Isolator made by Texas Instruments in a SOIC-8 package with 8 pins. -40℃~+125℃ 1 1 11ns 150kV/us 3000 50Mbps High Level SOIC-8 Digital Isolators ROHS.
PCBKit's library has its KiCad symbol (Isolator:ISO6721BD, from KiCad's library) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 7,076 are in stock at JLCPCB (part C5216430). 3 open-source boards in 2 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
21- Supply, least
- 1.71 V · VCC1, recommended operating minimum, 1.8 V operation · p. 6
- Supply, most
- 1.89 V · VCC1, recommended operating maximum, 1.8 V operation · p. 6
- Supply, least
- 2.25 V · VCC1, recommended operating minimum, 2.5 V to 5 V operation · p. 6
- Supply, most
- 5.5 V · VCC1, recommended operating maximum, 2.5 V to 5 V operation · p. 6
- Supply, absolute maximum
- 6 V · VCC1 to GND1, absolute maximum · p. 5
- Works from
- -40 °C · Ambient temperature minimum · p. 6
- Works up to
- 125 °C · Ambient temperature maximum · p. 6
- Junction, hottest
- 150 °C · Operating junction temperature maximum · p. 5
- A pin gives at most
- 15 mA · Output current absolute maximum magnitude · p. 5
- Takes working
- 3.8 mA · sum of ICC1 and ICC2 typical, 5 V, 1 Mbps, CL = 15 pF · p. 12
- Takes at most
- 13.4 mA · sum of ICC1 and ICC2 maximum, 5 V, 50 Mbps, CL = 15 pF · p. 12
- Junction to air (D (SOIC))
- 104.6 K/W · Junction-to-ambient thermal resistance · p. 7
- Junction to case (D (SOIC))
- 48.9 K/W · Junction-to-case (top) thermal resistance · p. 7
- Junction to board (D (SOIC))
- 52.9 K/W · Junction-to-board thermal resistance · p. 7
- Data rate, most
- 50 Mbit/s · Data rate maximum · p. 6
- Takes working
- 4.6 mA · sum of ICC1 and ICC2, typical, 3.3 V, 10 Mbps, all channels switching, CL = 15 pF · p. 14
- Takes at most
- 11 mA · sum of ICC1 and ICC2, max, 3.3 V, 50 Mbps, CL = 15 pF; largest provided · p. 14
- Edge
- 2.6 ns · typical output rise time, 5-V supply · p. 20
- Edge
- 1.6 ns · typical output rise time, 3.3-V supply · p. 20
- Edge
- 2 ns · typical output rise time, 2.5-V supply · p. 21
- Edge
- 2.7 ns · typical output rise time, 1.8-V supply · p. 21
What it is and has
16- Data rate
- 50 Mbps · p. 1
- Package
- Narrow-SOIC (D-8) · p. 1
- Propagation delay
- 11 ns typical · p. 1
- Common mode transient immunity
- ±150 kV/μs typical · p. 1
- Isolation rating
- Up to 3000 VRMS · p. 1
- Working voltage
- 450 VRMS · p. 1
- Level translation
- 1.71 V to 5.5 V · p. 1
- Certification
- DIN EN IEC 60747-17 (VDE 0884-17) · p. 1
- Certification
- UL 1577 component recognition program · p. 1
- Certification
- IEC 62368-1, IEC 61010-1, IEC 60601-1 · p. 1
- Certification
- GB 4943.1 · p. 1
- Channels
- 2; 1 Forward, 1 Reverse · p. 27
- Default output state
- High · p. 27
- Package
- D-8 · p. 27
- Rated isolation
- 3000 VRMS / 4242 VPK · p. 27
- Protection
- ESD protection for input and output signal pins and inter-chip bond pads · p. 27
Around it
2- cap 0.1 µF
- between VCC1 and GND1; Decoupling capacitor; circuit hook-up specifies 2 mm maximum from VCC1. · p. 31
- cap 0.1 µF
- between VCC2 and GND2; Decoupling capacitor; circuit hook-up specifies 2 mm maximum from VCC2. · p. 31
Specifications
141| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply Voltage (2) | VCC1 to GND1 | min -0.5 · max 6 V | 5 |
| Supply Voltage (2) | VCC2 to GND2 | min -0.5 · max 6 V | 5 |
| Input/Output Voltage | INx to GNDx; maximum VCCX + 0.5 V, not exceeding 6 V | min -0.5 V | 5 |
| Input/Output Voltage | OUTx to GNDx; maximum VCCX + 0.5 V, not exceeding 6 V | min -0.5 V | 5 |
| Output Current Io | min -15 · max 15 mA | 5 | |
| Operating junction temperature TJ | max 150 °C | 5 | |
| Storage temperature Tstg | min -65 · max 150 °C | 5 | |
| Electrostatic discharge V(ESD) | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins; ±6000 V | max 6000 V | 5 |
| Electrostatic discharge V(ESD) | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins; ±1500 V | max 1500 V | 5 |
| Electrostatic discharge V(ESD) | Contact discharge per IEC 61000-4-2; isolation barrier withstand test; ±8000 V | max 8000 V | 5 |
| Supply Voltage Side 1 VCC1 | VCC = 1.8 V | min 1.71 · max 1.89 V | 6 |
| Supply Voltage Side 1 VCC1 | VCC = 2.5 V to 5 V | min 2.25 · max 5.5 V | 6 |
| Supply Voltage Side 2 VCC2 | VCC = 1.8 V | min 1.71 · max 1.89 V | 6 |
| Supply Voltage Side 2 VCC2 | VCC = 2.5 V to 5 V | min 2.25 · max 5.5 V | 6 |
| UVLO threshold when supply voltage is rising VCC(UVLO+) | typ 1.53 · max 1.71 V | 6 | |
| UVLO threshold when supply voltage is falling VCC(UVLO-) | min 1.1 · typ 1.41 V | 6 | |
| Supply voltage UVLO hysteresis Vhys(UVLO) | min 0.08 · typ 0.13 V | 6 | |
| Low level Input voltage VIL | Maximum 0.3 x VCCI | min 0 V | 6 |
| High level output current IOH | VCCO = 5 V | min -4 mA | 6 |
| High level output current IOH | VCCO = 3.3 V | min -2 mA | 6 |
| High level output current IOH | VCCO = 2.5 V | min -1 mA | 6 |
| High level output current IOH | VCCO = 1.8 V | min -1 mA | 6 |
| Low level output current IOL | VCCO = 5 V | max 4 mA | 6 |
| Low level output current IOL | VCCO = 3.3 V | max 2 mA | 6 |
| Low level output current IOL | VCCO = 2.5 V | max 1 mA | 6 |
| Low level output current IOL | VCCO = 1.8 V | max 1 mA | 6 |
| Data Rate DR | min 0 · max 50 Mbps | 6 | |
| Ambient temperature TA | Nominal 25 °C | min -40 · max 125 °C | 6 |
| Junction-to-ambient thermal resistance RθJA | ISO672xB; D (SOIC), 8 PINS | typ 104.6 °C/W | 7 |
| Junction-to-case (top) thermal resistance RθJC(top) | ISO672xB; D (SOIC), 8 PINS | typ 48.9 °C/W | 7 |
| Junction-to-board thermal resistance RθJB | ISO672xB; D (SOIC), 8 PINS | typ 52.9 °C/W | 7 |
| Junction-to-top characterization parameter ψJT | ISO672xB; D (SOIC), 8 PINS | typ 7.9 °C/W | 7 |
| Junction-to-board characterization parameter ψJB | ISO672xB; D (SOIC), 8 PINS | typ 52.1 °C/W | 7 |
| Maximum power dissipation (both sides) PD | ISO6721B; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 25-MHz 50% duty cycle square wave | max 73 mW | 7 |
| Maximum power dissipation (side-1) PD1 | ISO6721B; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 25-MHz 50% duty cycle square wave | max 37 mW | 7 |
| Maximum power dissipation (side-2) PD2 | ISO6721B; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 25-MHz 50% duty cycle square wave | max 37 mW | 7 |
| External clearance(1) CLR | 8-D; side 1 to side 2 distance through air; >4 mm | min 4 mm | 8 |
| External creepage(1) CPG | 8-D; side 1 to side 2 distance across package surface; >4 mm | min 4 mm | 8 |
| Distance through the insulation DTI | 8-D; minimum internal gap (internal clearance); >17 um | min 17 um | 8 |
| Comparative tracking index CTI | 8-D; IEC 60112; UL 746A; >400 V | min 400 V | 8 |
| Maximum repetitive peak isolation voltage VIORM | 8-D; AC voltage (bipolar) | max 637 VPK | 8 |
| Maximum isolation working voltage VIOWM | 8-D; AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test; see Figure 9-8 | max 450 VRMS | 8 |
| Maximum isolation working voltage VIOWM | 8-D; DC voltage | max 637 VDC | 8 |
| Maximum transient isolation voltage VIOTM | 8-D; VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) | max 4242 VPK | 8 |
| Maximum impulse voltage(3) VIMP | 8-D; tested in air, 1.2/50-us waveform per IEC 62368-1 | max 5000 VPK | 8 |
| Maximum surge isolation voltage(4) VIOSM | 8-D; VIOSM ≥ 1.3 x VIMP; tested in oil (qualification test), 1.2/50-us waveform per IEC 62368-1 | max 6500 VPK | 8 |
| Apparent charge(5) qpd | 8-D; Method a: after I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s | max 5 pC | 8 |
| Apparent charge(5) qpd | 8-D; Method a: after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.3 × VIORM, tm = 10 s | max 5 pC | 8 |
| Apparent charge(5) qpd | 8-D; Method b: routine test (100% production) and preconditioning (type test); Vini = 1.2 x VIOTM, tini = 1 s; Vpd(m) = 1.5 x VIORM, tm = 1 s (method b1) or Vpd(m) = Vini, tm = tini (method b2) | max 5 pC | 8 |
| Barrier capacitance, input to output(6) CIO | 8-D; VIO = 0.4 × sin (2 πft), f = 1 MHz; approximately 0.5 pF | typ 0.5 pF | 8 |
| Withstand isolation voltage VISO | 8-D; UL 1577; VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) | max 3000 VRMS | 8 |
| Safety input, output, or supply current (1) IS | D-8 PACKAGE - ISO672xB; RθJA = 104.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | max 217.2 mA | 10 |
| Safety input, output, or supply current (1) IS | D-8 PACKAGE - ISO672xB; RθJA = 104.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | max 332 mA | 10 |
| Safety input, output, or supply current (1) IS | D-8 PACKAGE - ISO672xB; RθJA = 104.6°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C | max 434.5 mA | 10 |
| Safety input, output, or supply current (1) IS | D-8 PACKAGE - ISO672xB; RθJA = 104.6°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C | max 628.9 mA | 10 |
| Safety input, output, or total power (1) PS | D-8 PACKAGE - ISO672xB; RθJA = 104.6°C/W, TJ = 150°C, TA = 25°C | max 1195 mW | 10 |
| Maximum safety temperature (1) TS | D-8 PACKAGE - ISO672xB | max 150 °C | 10 |
| Low-level output voltage VOL | VCC1 = VCC2 = 5 V ± 10%; IOL = 4 mA | max 0.4 V | 12 |
| High-level input current IIH | VCC1 = VCC2 = 5 V ± 10%; VIH = VCCI at INx | max 10 uA | 12 |
| Low-level input current IIL | VCC1 = VCC2 = 5 V ± 10%; VIL = 0 V at INx | min -10 uA | 12 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 5 V ± 10%; VI = VCC or 0 V, VCM = 1200 V | min 100 · typ 150 kV/us | 12 |
| Input Capacitance (2) Ci | VI = VCC/2 + 0.4×sin(2πft), f = 2 MHz, VCC = 5 V; measured from input pin to same side ground | typ 2.8 pF | 12 |
| Supply current - DC signal (2) ICC1, ICC2 | ISO6721B; each supply; VCC1 = VCC2 = 5 V ± 10%; VI = VCCI | typ 1.2 · max 2.1 mA | 12 |
| Supply current - DC signal (2) ICC1, ICC2 | ISO6721B; each supply; VCC1 = VCC2 = 5 V ± 10%; VI = 0 V | typ 2.3 · max 3.5 mA | 12 |
| Supply current - AC signal (3) ICC1, ICC2 | ISO6721B; each supply; VCC1 = VCC2 = 5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps | typ 1.9 · max 2.9 mA | 12 |
| Supply current - AC signal (3) ICC1, ICC2 | ISO6721B; each supply; VCC1 = VCC2 = 5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps | typ 2.5 · max 3.6 mA | 12 |
| Supply current - AC signal (3) ICC1, ICC2 | ISO6721B; each supply; VCC1 = VCC2 = 5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 50 Mbps | typ 5.2 · max 6.7 mA | 12 |
| Low-level output voltage VOL | VCC1 = VCC2 = 3.3 V ± 10%; IOL = 2mA; See Figure 7-1 | max 0.2 V | 14 |
| High-level input current IIH | VCC1 = VCC2 = 3.3 V ± 10%; VIH = VCCI at INx | max 10 uA | 14 |
| Low-level input current IIL | VCC1 = VCC2 = 3.3 V ± 10%; VIL = 0 V at INx | min -10 uA | 14 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 3.3 V ± 10%; VI = VCC or 0 V, VCM = 1200 V | min 100 · typ 150 kV/us | 14 |
| Input Capacitance Ci | VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 3.3 V; measured from input pin to same side ground; See Figure 7-3 | typ 2.8 pF | 14 |
| Supply current - DC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 3.3 V ± 10%; VI = VCCI; each supply | typ 1.2 · max 2.1 mA | 14 |
| Supply current - DC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 3.3 V ± 10%; VI = 0 V; each supply | typ 2.3 · max 3.5 mA | 14 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 3.3 V ± 10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 1.8 · max 2.8 mA | 14 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 3.3 V ± 10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 2.3 · max 3.3 mA | 14 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 3.3 V ± 10%; 50 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 4.2 · max 5.5 mA | 14 |
| Low-level output voltage VOL | VCC1 = VCC2 = 2.5 V ± 10%; IOL = 1mA; See Figure 7-1 | max 0.1 V | 16 |
| High-level input current IIH | VCC1 = VCC2 = 2.5 V ± 10%; VIH = VCCI at INx | max 10 uA | 16 |
| Low-level input current IIL | VCC1 = VCC2 = 2.5 V ± 10%; VIL = 0 V at INx | min -10 uA | 16 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 2.5 V ± 10%; VI = VCC or 0 V, VCM = 1200 V | min 100 · typ 150 kV/us | 16 |
| Input Capacitance Ci | VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 2.5 V; measured from input pin to same side ground; See Figure 7-3 | typ 2.8 pF | 16 |
| Supply current - DC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 2.5 V ± 10%; VI = VCCI; each supply | typ 1.2 · max 2.1 mA | 16 |
| Supply current - DC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 2.5 V ± 10%; VI = 0 V; each supply | typ 2.3 · max 3.5 mA | 16 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 2.5 V ± 10%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 1.8 · max 2.8 mA | 16 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 2.5 V ± 10%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 2.1 · max 3.2 mA | 16 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 2.5 V ± 10%; 50 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 3.6 · max 4.9 mA | 16 |
| Low-level output voltage VOL | VCC1 = VCC2 = 1.8 V ± 5%; IOL = 1mA; See Figure 7-1 | max 0.1 V | 18 |
| High-level input current IIH | VCC1 = VCC2 = 1.8 V ± 5%; VIH = VCCI at INx | max 10 uA | 18 |
| Low-level input current IIL | VCC1 = VCC2 = 1.8 V ± 5%; VIL = 0 V at INx | min -10 uA | 18 |
| Common mode transient immunity CMTI | VCC1 = VCC2 = 1.8 V ± 5%; VI = VCC or 0 V, VCM = 1200 V | min 100 · typ 150 kV/us | 18 |
| Input Capacitance Ci | VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 1.8 V; measured from input pin to same side ground; See Figure 7-3 | typ 2.8 pF | 18 |
| Supply current - DC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 1.8 V ± 5%; VI = VCCI; each supply | typ 1.1 · max 2 mA | 18 |
| Supply current - DC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 1.8 V ± 5%; VI = 0 V; each supply | typ 2.1 · max 3.4 mA | 18 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 1.8 V ± 5%; 1 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 1.6 · max 2.7 mA | 18 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 1.8 V ± 5%; 10 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 1.9 · max 3 mA | 18 |
| Supply current - AC signal ICC1, ICC2 | ISO6721B; VCC1 = VCC2 = 1.8 V ± 5%; 50 Mbps; all channels switching with square wave clock input; CL = 15 pF; each supply | typ 3 · max 4.2 mA | 18 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 5 V ± 10%; See Figure 7-1 | typ 11 · max 18 ns | 20 |
| Propagation delay drift tP(dft) | VCC1 = VCC2 = 5 V ± 10% | typ 8 ps/℃ | 20 |
| Minimum pulse width tUI | VCC1 = VCC2 = 5 V ± 10%; See Figure 7-1 | min 20 ns | 20 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 5 V ± 10%; See Figure 7-1 | typ 0.2 · max 7 ns | 20 |
| Channel-to-channel output skew time tsk(o) | VCC1 = VCC2 = 5 V ± 10%; Same direction channels | max 6 ns | 20 |
| Part-to-part skew time tsk(p-p) | VCC1 = VCC2 = 5 V ± 10%; identical supply voltages, temperature, input signals and loads | max 6 ns | 20 |
| Output signal rise time tr | VCC1 = VCC2 = 5 V ± 10%; See Figure 7-1 | typ 2.6 · max 4.5 ns | 20 |
| Output signal fall time tf | VCC1 = VCC2 = 5 V ± 10%; See Figure 7-1 | typ 2.6 · max 4.5 ns | 20 |
| Time from UVLO to valid output data tPU | VCC1 = VCC2 = 5 V ± 10% | max 300 us | 20 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 5 V ± 10%; measured from the time VCC goes below 1.2V; See Figure 7-2 | typ 0.1 · max 0.3 us | 20 |
| Time interval error tie | VCC1 = VCC2 = 5 V ± 10%; 216 – 1 PRBS data at 50 Mbps | typ 1 ns | 20 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 3.3 V ± 10%; See Figure 7-1 | typ 11 · max 18 ns | 20 |
| Propagation delay drift tP(dft) | VCC1 = VCC2 = 3.3 V ± 10% | typ 9.2 ps/℃ | 20 |
| Minimum pulse width tUI | VCC1 = VCC2 = 3.3 V ± 10%; See Figure 7-1 | min 20 ns | 20 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 3.3 V ± 10%; See Figure 7-1 | typ 0.5 · max 7 ns | 20 |
| Channel-to-channel output skew time tsk(o) | VCC1 = VCC2 = 3.3 V ± 10%; Same direction channels | max 6 ns | 20 |
| Part-to-part skew time tsk(p-p) | VCC1 = VCC2 = 3.3 V ± 10%; identical supply voltages, temperature, input signals and loads | max 6 ns | 20 |
| Output signal rise time tr | VCC1 = VCC2 = 3.3 V ± 10%; See Figure 7-1 | typ 1.6 · max 3.2 ns | 20 |
| Output signal fall time tf | VCC1 = VCC2 = 3.3 V ± 10%; See Figure 7-1 | typ 1.6 · max 3.2 ns | 20 |
| Time from UVLO to valid output data tPU | VCC1 = VCC2 = 3.3 V ± 10% | max 300 us | 20 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 3.3 V ± 10%; measured from the time VCC goes below 1.2V; See Figure 7-2 | typ 0.1 · max 0.3 us | 20 |
| Time interval error tie | VCC1 = VCC2 = 3.3 V ± 10%; 216 – 1 PRBS data at 50 Mbps | typ 1 ns | 20 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 2.5 V ± 10%; See Figure 7-1 | typ 12 · max 20.5 ns | 21 |
| Propagation delay drift tP(dft) | VCC1 = VCC2 = 2.5 V ± 10% | typ 14.3 ps/℃ | 21 |
| Minimum pulse width tUI | VCC1 = VCC2 = 2.5 V ± 10%; See Figure 7-1 | min 20 ns | 21 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 2.5 V ± 10%; See Figure 7-1 | typ 0.6 · max 7.1 ns | 21 |
| Channel-to-channel output skew time tsk(o) | VCC1 = VCC2 = 2.5 V ± 10%; Same direction channels | max 6 ns | 21 |
| Part-to-part skew time tsk(p-p) | VCC1 = VCC2 = 2.5 V ± 10%; identical supply voltages, temperature, input signals and loads | max 6.1 ns | 21 |
| Output signal rise time tr | VCC1 = VCC2 = 2.5 V ± 10%; See Figure 7-1 | typ 2 · max 4 ns | 21 |
| Output signal fall time tf | VCC1 = VCC2 = 2.5 V ± 10%; See Figure 7-1 | typ 2 · max 4 ns | 21 |
| Time from UVLO to valid output data tPU | VCC1 = VCC2 = 2.5 V ± 10% | max 300 us | 21 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 2.5 V ± 10%; measured from the time VCC goes below 1.2V; See Figure 7-2 | typ 0.1 · max 0.3 us | 21 |
| Time interval error tie | VCC1 = VCC2 = 2.5 V ± 10%; 216 – 1 PRBS data at 50 Mbps | typ 1 ns | 21 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 1.8 V ± 5%; See Figure 7-1 | typ 15 · max 24 ns | 21 |
| Propagation delay drift tP(dft) | VCC1 = VCC2 = 1.8 V ± 5% | typ 15.2 ps/℃ | 21 |
| Minimum pulse width tUI | VCC1 = VCC2 = 1.8 V ± 5%; See Figure 7-1 | min 20 ns | 21 |
| Pulse width distortion(1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 1.8 V ± 5%; See Figure 7-1 | typ 0.7 · max 8.2 ns | 21 |
| Channel-to-channel output skew time tsk(o) | VCC1 = VCC2 = 1.8 V ± 5%; Same direction channels | max 6 ns | 21 |
| Part-to-part skew time tsk(p-p) | VCC1 = VCC2 = 1.8 V ± 5%; identical supply voltages, temperature, input signals and loads | max 8.8 ns | 21 |
| Output signal rise time tr | VCC1 = VCC2 = 1.8 V ± 5%; See Figure 7-1 | typ 2.7 · max 5.3 ns | 21 |
| Output signal fall time tf | VCC1 = VCC2 = 1.8 V ± 5%; See Figure 7-1 | typ 2.7 · max 5.3 ns | 21 |
| Time from UVLO to valid output data tPU | VCC1 = VCC2 = 1.8 V ± 5% | max 300 us | 21 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 1.8 V ± 5%; measured from the time VCC goes below 1.2V; See Figure 7-2 | typ 0.1 · max 0.3 us | 21 |
| Time interval error tie | VCC1 = VCC2 = 1.8 V ± 5%; 216 – 1 PRBS data at 50 Mbps | typ 1 ns | 21 |
Pins, by the datasheet
8- 1 VCC1
- Power supply, VCC1. · p. 4
- 2 OUTA
- Output, channel A. · p. 4
- 3 INB
- Input, channel B. · p. 4
- 4 GND1
- Ground connection for VCC1. · p. 4
- 5 GND2
- Ground connection for VCC2. · p. 4
- 6 OUTB
- Output, channel B. · p. 4
- 7 INA
- Input, channel A. · p. 4
- 8 VCC2
- Power supply, VCC2. · p. 4
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8
ADUM1201ARZ-RL7
SOIC-8-40℃~+105℃ 1 1 1Mbps 2.7V~5.5V 2.7V~5.5V 2500 25kV/us 50ns Bidirectional signal isolation、Multi-voltage domain interface、Power-on reset SOIC-8 Digital Isolators ROHSAnalog DevicesDigital IsolatorsCA-IS3720HS
SOIC-8-40℃~+125℃ 0 100kV/us 150Mbps 2 2 2.5V~5.5V 2.5V~5.5V 3750 8ns Fail-safe output High Level SOIC-8 Digital Isolators ROHSChipanalogDigital IsolatorsCA-IS3721HS
SOIC-8-40℃~+125℃ 1 1 100kV/us 150Mbps 2 2.5V~5.5V 2.5V~5.5V 3750 8ns Fail-safe output High Level SOIC-8 Digital Isolators ROHSChipanalogDigital IsolatorsISO7721D
SOIC-8-55℃~+125℃ 1 1 100Mbps 100kV/us 11ns 2.25V~5.5V 2.25V~5.5V 5000 Fail-safe output High Level SOIC-8 Digital Isolators ROHSTexas InstrumentsDigital IsolatorsΠ120U31
SOIC-8-40℃~+125℃ 0 150Kbps 150kV/us 2 3000 3V~5.5V 3V~5.5V 4.5us Fail-safe output High Level SOIC-8 Digital Isolators ROHS2Pai SemiDigital IsolatorsΠ122M31
SOIC-8-40℃~+125℃ 1 1 10Mbps 3000 3V~5.5V 3V~5.5V 75kV/us 8ns Fail-safe output、Multi-voltage domain interface High Level SOIC-8 Digital Isolators ROHS2Pai SemiDigital IsolatorsCA-IS3721CHS
SOIC-8Digital IsolatorsChipanalogΠ120M30
SOIC-8-40℃~+125℃ 0 10Mbps 2 3000 3V~5.5V 3V~5.5V 75kV/us 8ns Fail-safe output、Multi-voltage domain interface Low Level SOIC-8 Digital Isolators ROHS2Pai SemiDigital Isolators
Questions
Is there a KiCad symbol and footprint for the ISO6721BD?
Yes. The symbol is Isolator:ISO6721BD and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the ISO6721BD?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the ISO6721BD datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the ISO6721BD?
JLCPCB lists it as part C5216430, with 7,076 in stock; the sellers' links on this page open their listings.
What can replace the ISO6721BD?
Parts like it in the library: the ADUM1201ARZ-RL7 by Analog Devices, the CA-IS3720HS by Chipanalog, the CA-IS3721HS by Chipanalog and the ISO7721D by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the ISO6721BD?
3 boards in 2 repositories on GitHub; the most starred are listed on this page, with their KiCad files.