2 layers50 × 35 mm
Bms4 f051
GyrocopterLLC/bms4-rust
Battery management system (bms) for 4 series Li-Ion cells programmed in Rust
63 parts1MIT
Overview
The ISO7721D is a digital Isolator made by Texas Instruments in a SOIC-8 package with 8 pins. -55℃~+125℃ 1 1 100Mbps 100kV/us 11ns 2.25V~5.5V 2.25V~5.5V 5000 Fail-safe output High Level SOIC-8 Digital Isolators ROHS.
PCBKit's library has its KiCad symbol (Isolator:ISO7721D, from KiCad's library) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 23,332 are in stock at JLCPCB (part C366164). 2 open-source boards in 2 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
18- Supply, least
- 2.25 V · VCC1, recommended operating min · p. 5
- Supply, most
- 5.5 V · VCC1, recommended operating max · p. 5
- Supply, absolute maximum
- 6 V · VCC1, absolute max · p. 5
- Works from
- -55 °C · Ambient temperature min · p. 5
- Works up to
- 125 °C · Ambient temperature max · p. 5
- Junction, hottest
- 150 °C · Junction temperature max · p. 5
- A pin gives at most
- 15 mA · Output source or sink current absolute max · p. 5
- Data rate, most
- 100 Mbit/s · Signaling rate max · p. 5
- Junction to air (D (SOIC))
- 137.7 K/W · Junction-to-ambient thermal resistance · p. 6
- Junction to case (D (SOIC))
- 54.9 K/W · Junction-to-case(top) thermal resistance · p. 6
- Junction to board (D (SOIC))
- 71.7 K/W · Junction-to-board thermal resistance · p. 6
- Takes working
- 3.4 mA · sum of ICC1 and ICC2 typical, 5 V, 1 Mbps, all channels switching, CL = 15 pF · p. 10
- Takes at most
- 18 mA · sum of ICC1 and ICC2 max, 5 V, 100 Mbps, all channels switching, CL = 15 pF · p. 10
- Takes working
- 3.2 mA · sum of ICC1 and ICC2, typical, 3.3 V, 1 Mbps, CL = 15 pF · p. 11
- Takes at most
- 14 mA · sum of ICC1 and ICC2, max, 3.3 V, 100 Mbps, CL = 15 pF · p. 11
- Edge
- 1.8 ns · typical output rise time, 5-V supply · p. 13
- Edge
- 700 ps · typical output rise time, 3.3-V supply · p. 13
- Edge
- 1 ns · typical output rise time, 2.5-V supply · p. 13
What it is and has
8- Maximum signaling rate
- 100 Mbps · p. 1
- Level translation
- 2.25 V to 5.5 V · p. 1
- Propagation delay
- 11 ns typical, 5 V supply · p. 1
- Common-mode transient immunity
- ±100 kV/μs typical · p. 1
- Isolation barrier lifetime
- > 40 years · p. 1
- Channels
- 1 Forward, 1 Reverse · p. 19
- Default output state
- High · p. 19
- Rated isolation
- D-8: 3000 VRMS / 4242 VPK · p. 19
Around it
2- cap 0.1 µF
- between VCC1 and GND1; Decoupling capacitor · p. 22
- cap 0.1 µF
- between VCC2 and GND2; Decoupling capacitor · p. 22
Specifications
102| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage VCC1, VCC2 | min -0.5 · max 6 V | 5 | |
| Voltage at INx, OUTx V | Maximum voltage must not exceed 6 V | min -0.5 V | 5 |
| Output current IO | min -15 · max 15 mA | 5 | |
| Junction temperature TJ | max 150 °C | 5 | |
| Storage temperature Tstg | min -65 · max 150 °C | 5 | |
| Electrostatic discharge VESD | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins | max 6000 V | 5 |
| Electrostatic discharge VESD | Charged device model (CDM), per JEDEC specification JESD22-C101, all pins | max 1500 V | 5 |
| Supply voltage VCC1, VCC2 | min 2.25 · max 5.5 V | 5 | |
| UVLO threshold when supply voltage is rising VCC(UVLO+) | typ 2 · max 2.25 V | 5 | |
| UVLO threshold when supply voltage is falling VCC(UVLO-) | min 1.7 · typ 1.8 V | 5 | |
| Supply voltage UVLO hysteresis VHYS(UVLO) | min 100 · typ 200 mV | 5 | |
| High-level output current IOH | VCCO = 5 V | min -4 mA | 5 |
| High-level output current IOH | VCCO = 3.3 V | min -2 mA | 5 |
| High-level output current IOH | VCCO = 2.5 V | min -1 mA | 5 |
| Low-level output current IOL | VCCO = 5 V | max 4 mA | 5 |
| Low-level output current IOL | VCCO = 3.3 V | max 2 mA | 5 |
| Low-level output current IOL | VCCO = 2.5 V | max 1 mA | 5 |
| Low-level input voltage VIL | VCCI = Input-side VCC | min 0 V | 5 |
| Signaling rate DR | min 0 · max 100 Mbps | 5 | |
| Ambient temperature TA | min -55 · typ 25 · max 125 °C | 5 | |
| Junction-to-ambient thermal resistance RθJA | D (SOIC), 8 PINS | typ 137.7 °C/W | 6 |
| Junction-to-case(top) thermal resistance RθJC(top) | D (SOIC), 8 PINS | typ 54.9 °C/W | 6 |
| Junction-to-board thermal resistance RθJB | D (SOIC), 8 PINS | typ 71.7 °C/W | 6 |
| Junction-to-top characterization parameter ψJT | D (SOIC), 8 PINS | typ 7.1 °C/W | 6 |
| Junction-to-board characterization parameter ψJB | D (SOIC), 8 PINS | typ 70.7 °C/W | 6 |
| Maximum power dissipation PD | ISO7721; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave | max 100 mW | 6 |
| Maximum power dissipation by side-1 PD1 | ISO7721; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave | max 50 mW | 6 |
| Maximum power dissipation by side-2 PD2 | ISO7721; VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave | max 50 mW | 6 |
| External clearance CLR | D; Shortest terminal-to-terminal distance through air | typ 4 mm | 7 |
| External creepage CPG | D; Shortest terminal-to-terminal distance across the package surface | typ 4 mm | 7 |
| Distance through the insulation DTI | D; Minimum internal gap (internal clearance) | typ 21 um | 7 |
| Maximum repetitive peak isolation voltage VIORM | D; AC voltage (bipolar); DIN V VDE V 0884-11:2017-01 | max 637 VPK | 7 |
| Maximum working isolation voltage VIOWM | D; AC voltage; Time dependent dielectric breakdown (TDDB) test | max 450 VRMS | 7 |
| Maximum working isolation voltage VIOWM | D; DC voltage | max 637 VDC | 7 |
| Maximum transient isolation voltage VIOTM | D; VTEST = VIOTM, t = 60 s (qualification); t = 1 s (100% production) | max 4242 VPK | 7 |
| Maximum surge isolation voltage VIOSM | D; Test method per IEC 60065, 1.2/50 us waveform, VTEST = 1.6 × VIOSM (qualification) | max 5000 VPK | 7 |
| Apparent charge qpd | D; Method a, After Input/Output safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s | max 5 pC | 7 |
| Apparent charge qpd | D; Method a, After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s | max 5 pC | 7 |
| Apparent charge qpd | D; Method b1; At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM, tm = 1 s | max 5 pC | 7 |
| Barrier capacitance, input to output CIO | D; VIO = 0.4 × sin (2πft), f = 1 MHz; approximate value | typ 0.5 pF | 7 |
| Pollution degree | D; value 2 | typ 2 | 7 |
| Withstanding isolation voltage VISO | D; UL 1577; VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) | max 3000 VRMS | 7 |
| Safety input, output, or supply current IS | D-8 PACKAGE; RθJA = 137.7 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 5 | max 165 mA | 9 |
| Safety input, output, or supply current IS | D-8 PACKAGE; RθJA = 137.7 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 5 | max 252 mA | 9 |
| Safety input, output, or supply current IS | D-8 PACKAGE; RθJA = 137.7 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 5 | max 330 mA | 9 |
| Safety input, output, or total power PS | D-8 PACKAGE; RθJA = 137.7 °C/W, TJ = 150°C, TA = 25°C, see Figure 6 | max 908 mW | 9 |
| Maximum safety temperature TS | D-8 PACKAGE | max 150 °C | 9 |
| High-level output voltage VOH | VCC1 = VCC2 = 5 V ± 10%; IOH = –4 mA; see Figure 15 | typ 4.8 V | 10 |
| Low-level output voltage VOL | VCC1 = VCC2 = 5 V ± 10%; IOL = 4 mA; see Figure 15 | typ 0.2 · max 0.4 V | 10 |
| High-level input current IIH | VCC1 = VCC2 = 5 V ± 10%; VIH = VCCI at INx | max 10 uA | 10 |
| Low-level input current IIL | VCC1 = VCC2 = 5 V ± 10%; VIL = 0 V at INx | min -10 uA | 10 |
| Common-mode transient immunity CMTI | VCC1 = VCC2 = 5 V ± 10%; VI = VCCI or 0 V, VCM = 1200 V; see Figure 17 | min 85 · typ 100 kV/us | 10 |
| Input Capacitance CI | VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V; measured from input pin to ground | typ 2 pF | 10 |
| Supply current - DC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 5 V ± 10%; VI = VCCI; each supply | typ 1 · max 1.6 mA | 10 |
| Supply current - DC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 5 V ± 10%; VI = 0 V; each supply | typ 2.2 · max 3.2 mA | 10 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps; each supply | typ 1.7 · max 2.4 mA | 10 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps; each supply | typ 2.2 · max 3 mA | 10 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps; each supply | typ 7.3 · max 9 mA | 10 |
| High-level output voltage VOH | VCC1 = VCC2 = 3.3 V ± 10%; IOH = –2 mA; see Figure 15; minimum VCCO – 0.3 V | typ 3.2 V | 11 |
| Low-level output voltage VOL | VCC1 = VCC2 = 3.3 V ± 10%; IOL = 2 mA; see Figure 15 | typ 0.1 · max 0.3 V | 11 |
| High-level input current IIH | VCC1 = VCC2 = 3.3 V ± 10%; VIH = VCCI at INx | max 10 uA | 11 |
| Low-level input current IIL | VCC1 = VCC2 = 3.3 V ± 10%; VIL = 0 V at INx | min -10 uA | 11 |
| Common-mode transient immunity CMTI | VCC1 = VCC2 = 3.3 V ± 10%; VI = VCCI or 0 V, VCM = 1200 V; see Figure 17 | min 85 · typ 100 kV/us | 11 |
| Supply current - DC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 3.3 V ± 10%; VI = VCCI; values per supply | typ 1 · max 1.6 mA | 11 |
| Supply current - DC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 3.3 V ± 10%; VI = 0 V; values per supply | typ 2.2 · max 3.2 mA | 11 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 3.3 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps; values per supply | typ 1.6 · max 2.4 mA | 11 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 3.3 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps; values per supply | typ 2 · max 2.8 mA | 11 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 3.3 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps; values per supply | typ 5.6 · max 7 mA | 11 |
| High-level output voltage VOH | VCC1 = VCC2 = 2.5 V ± 10%; IOH = –1 mA; see Figure 15; minimum VCCO – 0.2 V | typ 2.45 V | 12 |
| Low-level output voltage VOL | VCC1 = VCC2 = 2.5 V ± 10%; IOL = 1 mA; see Figure 15 | typ 0.05 · max 0.2 V | 12 |
| High-level input current IIH | VCC1 = VCC2 = 2.5 V ± 10%; VIH = VCCI at INx | max 10 uA | 12 |
| Low-level input current IIL | VCC1 = VCC2 = 2.5 V ± 10%; VIL = 0 V at INx | min -10 uA | 12 |
| Common-mode transient immunity CMTI | VCC1 = VCC2 = 2.5 V ± 10%; VI = VCCI or 0 V, VCM = 1200 V; see Figure 17 | min 85 · typ 100 kV/us | 12 |
| Supply current - DC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 2.5 V ± 10%; VI = VCCI; values per supply | typ 1 · max 1.6 mA | 12 |
| Supply current - DC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 2.5 V ± 10%; VI = 0 V; values per supply | typ 2.2 · max 3.2 mA | 12 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 2.5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 1 Mbps; values per supply | typ 1.6 · max 2.4 mA | 12 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 2.5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 10 Mbps; values per supply | typ 1.9 · max 2.7 mA | 12 |
| Supply current - AC signal ICC1, ICC2 | ISO7721; VCC1 = VCC2 = 2.5 V ± 10%; all channels switching with square wave clock input; CL = 15 pF; 100 Mbps; values per supply | typ 4.6 · max 6 mA | 12 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 5 V ± 10%; see Figure 15 | min 6 · typ 11 · max 16 ns | 13 |
| Pulse width distortion (1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 5 V ± 10%; see Figure 15 | typ 0.5 · max 4.9 ns | 13 |
| Channel-to-channel output skew time (2) tsk(o) | VCC1 = VCC2 = 5 V ± 10%; Same direction channels | max 4 ns | 13 |
| Part-to-part skew time (3) tsk(pp) | VCC1 = VCC2 = 5 V ± 10% | max 4.5 ns | 13 |
| Output signal rise time tr | VCC1 = VCC2 = 5 V ± 10%; see Figure 15 | typ 1.8 · max 3.9 ns | 13 |
| Output signal fall time tf | VCC1 = VCC2 = 5 V ± 10%; see Figure 15 | typ 1.9 · max 3.9 ns | 13 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 5 V ± 10%; measured from the time VCC goes below 1.7 V; see Figure 16 | typ 0.1 · max 0.3 us | 13 |
| Time interval error tie | VCC1 = VCC2 = 5 V ± 10%; 216 – 1 PRBS data at 100 Mbps | typ 1 ns | 13 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 3.3 V ± 10%; see Figure 15 | min 6 · typ 11 · max 16 ns | 13 |
| Pulse width distortion (1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 3.3 V ± 10%; see Figure 15 | typ 0.5 · max 5 ns | 13 |
| Channel-to-channel output skew time (2) tsk(o) | VCC1 = VCC2 = 3.3 V ± 10%; Same direction channels | max 4.1 ns | 13 |
| Part-to-part skew time (3) tsk(pp) | VCC1 = VCC2 = 3.3 V ± 10% | max 4.5 ns | 13 |
| Output signal rise time tr | VCC1 = VCC2 = 3.3 V ± 10%; see Figure 15 | typ 0.7 · max 3 ns | 13 |
| Output signal fall time tf | VCC1 = VCC2 = 3.3 V ± 10%; see Figure 15 | typ 0.7 · max 3 ns | 13 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 3.3 V ± 10%; measured from the time VCC goes below 1.7 V; see Figure 16 | typ 0.1 · max 0.3 us | 13 |
| Time interval error tie | VCC1 = VCC2 = 3.3 V ± 10%; 216 – 1 PRBS data at 100 Mbps | typ 1 ns | 13 |
| Propagation delay time tPLH, tPHL | VCC1 = VCC2 = 2.5 V ± 10%; see Figure 15 | min 7.5 · typ 12 · max 18.5 ns | 13 |
| Pulse width distortion (1) |tPHL – tPLH| PWD | VCC1 = VCC2 = 2.5 V ± 10%; see Figure 15 | typ 0.5 · max 5.1 ns | 13 |
| Channel-to-channel output skew time tsk(o) | VCC1 = VCC2 = 2.5 V ± 10%; Same direction channels | max 4.1 ns | 13 |
| Part-to-part skew time (3) tsk(pp) | VCC1 = VCC2 = 2.5 V ± 10% | max 4.6 ns | 13 |
| Output signal rise time tr | VCC1 = VCC2 = 2.5 V ± 10%; see Figure 15 | typ 1 · max 3.5 ns | 13 |
| Output signal fall time tf | VCC1 = VCC2 = 2.5 V ± 10%; see Figure 15 | typ 1 · max 3.5 ns | 13 |
| Default output delay time from input power loss tDO | VCC1 = VCC2 = 2.5 V ± 10%; measured from the time VCC goes below 1.7 V; see Figure 16 | typ 0.1 · max 0.3 us | 13 |
| Time interval error tie | VCC1 = VCC2 = 2.5 V ± 10%; PRBS data at 100 Mbps | typ 1 ns | 13 |
Pins, by the datasheet
8- 1 VCC1
- Power supply, VCC1. · p. 4
- 2 OUTA
- Output, channel A. · p. 4
- 3 INB
- Input, channel B. · p. 4
- 4 GND1
- Ground connection for VCC1. · p. 4
- 5 GND2
- Ground connection for VCC2. · p. 4
- 6 OUTB
- Output, channel B. · p. 4
- 7 INA
- Input, channel A. · p. 4
- 8 VCC2
- Power supply, VCC2. · p. 4
Parameters
22- CMTI(kV/us)
- 100kV/us
- Current - Supply
- 3.4mA
- Current - Supply(Max)
- 18mA
- Data Rate(Max)
- 100Mbps
- Default Output
- High Level
- Features
- Fail-safe output
- Isolation Voltage(Vrms)
- 5000
- Junction Temperature(Max)
- 150℃
- Number of Channels
- 2
- Number of Forward Channels
- 1
- Number of Reverse Channels
- 1
- Operating Temperature
- -55℃~+125℃
- Output Current per Pin(Max)
- 15mA
- Propagation Delay(tpd)
- 11ns
- Rise Time
- 1.8ns
- Thermal Resistance(Junction to Ambient)
- 137.7℃/W
- Thermal Resistance(Junction to Board)
- 71.7℃/W
- Thermal Resistance(Junction to Case)
- 54.9℃/W
- Voltage - Supply
- 2.25V~5.5V
- Voltage - Supply(Absolute Max)
- 6V
- Voltage - Supply(VCCA)
- 2.25V~5.5V
- Voltage - Supply(VCCB)
- 2.25V~5.5V
Order codes
2- ISO7721DLCSC C2878283
- ISO7721DRLCSC C366164
Pinout
8| Pin | Name | Type |
|---|---|---|
| 1 | VCC1 | Power in |
| 2 | OUTA | Output |
| 3 | INB | Input |
| 4 | GND1 | Power in |
| 5 | GND2 | Power in |
| 6 | OUTB | Output |
| 7 | INA | Input |
| 8 | VCC2 | Power in |
Open-source boards using it
All 2- 2 layers104 × 76 mm
Sdc ntc emulator
bl1ndc4m3l/sdc-ntc-emulator
SDC3-40 NTC emulator for remote temperature setpoint
58 parts
Show this part on your page
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Is there a KiCad symbol and footprint for the ISO7721D?
Yes. The symbol is Isolator:ISO7721D and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the ISO7721D?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the ISO7721D datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the ISO7721D?
JLCPCB lists it as part C366164, with 23,332 in stock; the sellers' links on this page open their listings.
What can replace the ISO7721D?
Parts like it in the library: the ADUM1201ARZ-RL7 by Analog Devices, the CA-IS3720HS by Chipanalog, the CA-IS3721HS by Chipanalog and the Π120U31 by 2Pai Semi. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the ISO7721D?
2 boards in 2 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
Parts like it
8
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