2 layers
INA826AID
Texas InstrumentsExtended
-18V~-1.5V、1.5V~18V -40℃~+125℃ 1 100dB 104dB 150uV 16mA 18nV/√Hz@1kHz 1MHz 1V/us 200uA 2uV/℃ 35nA 36V 3V~36V 5nA Rail-to-Rail Output SOIC-8 Instrumentation Amplifiers ROHS
- Part id
- ti/INA826AID
- Category
- Instrumentation Amplifiers
- Package
- SOIC-8
- Pins
- 8
- In stock
- 9,032 at JLCPCB (C38433)
- Used on
- 4 open-source boards
Overview
The INA826AID is an instrumentation Amplifier made by Texas Instruments in a SOIC-8 package with 8 pins. -18V~-1.5V、1.5V~18V -40℃~+125℃ 1 100dB 104dB 150uV 16mA 18nV/√Hz@1kHz 1MHz 1V/us 200uA 2uV/℃ 35nA 36V 3V~36V 5nA Rail-to-Rail Output SOIC-8 Instrumentation Amplifiers ROHS.
PCBKit's library has its KiCad symbol (Celestial_Opamp:TI INA826, from Altium's library) and its footprint (Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, from KiCad's library), ready for a KiCad board. 9,032 are in stock at JLCPCB (part C38433). 4 open-source boards in 4 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
12- Supply, least
- 3 V · +VS, recommended operating single supply min · p. 5
- Supply, most
- 36 V · +VS, recommended operating single supply max · p. 5
- Supply, least
- 1.5 V · ±VS, recommended operating dual supply magnitude min · p. 5
- Supply, most
- 18 V · ±VS, recommended operating dual supply magnitude max · p. 5
- Works from
- -40 °C · TA, specified operating min · p. 5
- Works up to
- 125 °C · TA, specified operating max · p. 5
- Junction, hottest
- 175 °C · TJ, absolute maximum · p. 5
- Takes working
- 200 µA · IQ, VIN = 0 V, typical · p. 7
- Takes at most
- 300 µA · IQ, TA = –40°C to +125°C, max · p. 7
- Junction to air (D (SOIC))
- 141.4 K/W · junction-to-ambient thermal resistance · p. 5
- Junction to case (D (SOIC))
- 75.4 K/W · junction-to-case (top) thermal resistance · p. 5
- Junction to board (D (SOIC))
- 59.6 K/W · junction-to-board thermal resistance · p. 5
What it is and has
12- Input common-mode range
- Includes V– · p. 1
- Common-mode rejection
- 104 dB minimum, G = 10 · p. 1
- Common-mode rejection at 5 kHz
- 100 dB minimum, G = 10 · p. 1
- Power-supply rejection
- 100 dB minimum, G = 1 · p. 1
- Offset voltage
- 150 µV maximum · p. 1
- Gain drift
- 1 ppm/°C at G = 1; 35 ppm/°C at G > 1 · p. 1
- Noise
- 18 nV/√Hz, G ≥ 100 · p. 1
- Bandwidth
- 1 MHz at G = 1; 60 kHz at G = 100 · p. 1
- Protection
- Inputs protected up to ±40 V · p. 1
- Output
- Rail-to-rail · p. 1
- Supply current
- 200 µA · p. 1
- Package options
- 8-pin VSSOP, SOIC, and WSON · p. 1
Around it
9- res 49.4 kΩ
- between RG (2) and RG (3); Gain-setting resistor for desired gain 2 V/V; nearest 1% value 49.9 kΩ. · p. 20
- res 12.35 kΩ
- between RG (2) and RG (3); Gain-setting resistor for desired gain 5 V/V; nearest 1% value 12.4 kΩ. · p. 20
- res 5.489 kΩ
- between RG (2) and RG (3); Gain-setting resistor for desired gain 10 V/V; nearest 1% value 5.49 kΩ. · p. 20
- res 2.600 kΩ
- between RG (2) and RG (3); Gain-setting resistor for desired gain 20 V/V; nearest 1% value 2.61 kΩ. · p. 20
- res 1.008 kΩ
- between RG (2) and RG (3); Gain-setting resistor for desired gain 50 V/V; nearest 1% value 1 kΩ. · p. 20
- res 499 Ω
- between RG (2) and RG (3); Gain-setting resistor for desired gain 100 V/V; nearest 1% value 499 Ω. · p. 20
- res 248 Ω
- between RG (2) and RG (3); Gain-setting resistor for desired gain 200 V/V; nearest 1% value 249 Ω. · p. 20
- res 99 Ω
- between RG (2) and RG (3); Gain-setting resistor for desired gain 500 V/V; nearest 1% value 100 Ω. · p. 20
- res 49.5 Ω
- between RG (2) and RG (3); Gain-setting resistor for desired gain 1000 V/V; nearest 1% value 49.9 Ω. · p. 20
Specifications
75| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage | Over operating free-air temperature range | min -20 · max 20 V | 5 |
| Signal input pins | REF pin | min -20 · max 20 V | 5 |
| Temperature TA | Operating | min -50 · max 150 °C | 5 |
| Temperature TJ | Junction | max 175 °C | 5 |
| Temperature Tstg | Storage | min -65 · max 150 °C | 5 |
| Electrostatic discharge V(ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; ±2500 V | max 2500 V | 5 |
| Electrostatic discharge V(ESD) | Charged-device model (CDM), per JEDEC specification JESD22-C101; ±1500 V | max 1500 V | 5 |
| Electrostatic discharge V(ESD) | Machine model (MM); ±150 V | max 150 V | 5 |
| Supply voltage | Single-supply | min 3 · max 36 V | 5 |
| Supply voltage | Dual-supply; limits are ±1.5 V and ±18 V | min 1.5 · max 18 V | 5 |
| Specified temperature TA | Operating free-air temperature | min -40 · max 125 °C | 5 |
| Junction-to-ambient thermal resistance RθJA | D (SOIC), 8 PINS | typ 141.4 °C/W | 5 |
| Junction-to-case (top) thermal resistance RθJC(top) | D (SOIC), 8 PINS | typ 75.4 °C/W | 5 |
| Junction-to-board thermal resistance RθJB | D (SOIC), 8 PINS | typ 59.6 °C/W | 5 |
| Junction-to-top characterization parameter ψJT | D (SOIC), 8 PINS | typ 27.4 °C/W | 5 |
| Junction-to-board characterization parameter ψJB | D (SOIC), 8 PINS | typ 59.1 °C/W | 5 |
| Input stage offset voltage (1) VOSI | RTI; TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, G = 1 | typ 40 · max 150 uV | 6 |
| Input stage offset voltage (1) VOSI | vs temperature, TA = –40°C to +125°C | typ 0.4 · max 2 uV/°C | 6 |
| Output stage offset voltage (1) VOSO | RTI; TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, G = 1 | typ 200 · max 700 uV | 6 |
| Output stage offset voltage (1) VOSO | vs temperature, TA = –40°C to +125°C | typ 2 · max 10 uV/°C | 6 |
| Powersupply rejection ratio PSRR | G = 1, RTI | min 100 · typ 124 dB | 6 |
| Powersupply rejection ratio PSRR | G = 10, RTI | min 115 · typ 130 dB | 6 |
| Powersupply rejection ratio PSRR | G = 100, RTI | min 120 · typ 140 dB | 6 |
| Powersupply rejection ratio PSRR | G = 1000, RTI | min 120 · typ 140 dB | 6 |
| RFI filter, –3-dB frequency | TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, G = 1 | typ 20 MHz | 6 |
| Input overvoltage range | TA = –40°C to +125°C; ±40 V | max 40 V | 6 |
| Common-mode rejection ratio CMRR | At dc to 60 Hz, RTI; G = 1, VCM = (V–) to (V+) – 1 V | min 84 · typ 95 dB | 6 |
| Common-mode rejection ratio CMRR | At dc to 60 Hz, RTI; G = 10, VCM = (V–) to (V+) – 1 V | min 104 · typ 115 dB | 6 |
| Common-mode rejection ratio CMRR | At dc to 60 Hz, RTI; G = 100, VCM = (V–) to (V+) – 1 V | min 120 · typ 130 dB | 6 |
| Common-mode rejection ratio CMRR | At dc to 60 Hz, RTI; G = 1000, VCM = (V–) to (V+) – 1 V | min 120 · typ 130 dB | 6 |
| Common-mode rejection ratio CMRR | At dc to 60 Hz, RTI; G = 1, VCM = (V–) to (V+) – 1 V, TA = –40°C to +125°C | min 80 dB | 6 |
| Common-mode rejection ratio CMRR | At 5 kHz, RTI; G = 1, VCM = (V–) to (V+) – 1 V | min 84 dB | 6 |
| Common-mode rejection ratio CMRR | At 5 kHz, RTI; G = 10, VCM = (V–) to (V+) – 1 V | min 100 dB | 6 |
| Common-mode rejection ratio CMRR | At 5 kHz, RTI; G = 100, VCM = (V–) to (V+) – 1 V | min 105 dB | 6 |
| Common-mode rejection ratio CMRR | At 5 kHz, RTI; G = 1000, VCM = (V–) to (V+) – 1 V | min 105 dB | 6 |
| Input bias current IB | VCM = VS / 2 | typ 35 · max 65 nA | 6 |
| Input bias current IB | TA = –40°C to +125°C | max 95 nA | 6 |
| Input offset current IOS | VCM = VS / 2 | typ 0.7 · max 5 nA | 6 |
| Input offset current IOS | TA = –40°C to +125°C | max 10 nA | 6 |
| Input stage voltage noise (3) eNI | f = 1 kHz, G = 100, RS = 0 Ω | typ 18 · max 20 nV/√Hz | 6 |
| Input stage voltage noise (3) eNI | fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω | typ 0.52 uVPP | 6 |
| Output stage voltage noise eNO | f = 1 kHz, G = 1, RS = 0 Ω | typ 110 · max 115 nV/√Hz | 6 |
| Output stage voltage noise eNO | fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω | typ 3.3 uVPP | 6 |
| Noise current In | f = 1 kHz | typ 100 fA/√Hz | 6 |
| Noise current In | fB = 0.1 Hz to 10 Hz | typ 5 pAPP | 6 |
| Range of gain | TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V | min 1 · max 1000 V/V | 7 |
| Gain error GE | G = 1, VO = ±10 V; values are ± | typ 0.003 · max 0.015 % | 7 |
| Gain error GE | G = 10, VO = ±10 V; values are ± | typ 0.03 · max 0.15 % | 7 |
| Gain error GE | G = 100, VO = ±10 V; values are ± | typ 0.04 · max 0.15 % | 7 |
| Gain error GE | G = 1000, VO = ±10 V; values are ± | typ 0.04 · max 0.15 % | 7 |
| Gain vs temperature (4) | G = 1, TA = –40°C to +125°C; values are ± | typ 0.1 · max 1 ppm/°C | 7 |
| Gain vs temperature (4) | G > 1, TA = –40°C to +125°C; values are ±; excludes external RG effects | typ 10 · max 35 ppm/°C | 7 |
| Gain nonlinearity | G = 1 to 100, VO = –10 V to +10 V | typ 1 · max 5 ppm | 7 |
| Gain nonlinearity | G = 1000, VO = –10 V to +10 V | typ 5 · max 20 ppm | 7 |
| Load capacitance stability | TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, G = 1 | typ 1000 pF | 7 |
| Short-circuit current ISC | Continuous to VS / 2; typical ±16 mA | typ 16 mA | 7 |
| Bandwidth, –3 dB BW | G = 1 | typ 1 MHz | 7 |
| Bandwidth, –3 dB BW | G = 10 | typ 500 kHz | 7 |
| Bandwidth, –3 dB BW | G = 100 | typ 60 kHz | 7 |
| Bandwidth, –3 dB BW | G = 1000 | typ 6 kHz | 7 |
| Slew rate SR | G = 1, VO = ±14.5 V | typ 1 V/us | 7 |
| Slew rate SR | G = 100, VO = ±14.5 V | typ 1 V/us | 7 |
| Settling time tS | 0.01%; G = 1, VSTEP = 10 V | typ 12 us | 7 |
| Settling time tS | 0.01%; G = 10, VSTEP = 10 V | typ 12 us | 7 |
| Settling time tS | 0.01%; G = 100, VSTEP = 10 V | typ 24 us | 7 |
| Settling time tS | 0.01%; G = 1000, VSTEP = 10 V | typ 224 us | 7 |
| Settling time tS | 0.001%; G = 1, VSTEP = 10 V | typ 14 us | 7 |
| Settling time tS | 0.001%; G = 10, VSTEP = 10 V | typ 14 us | 7 |
| Settling time tS | 0.001%; G = 100, VSTEP = 10 V | typ 31 us | 7 |
| Settling time tS | 0.001%; G = 1000, VSTEP = 10 V | typ 278 us | 7 |
| Input impedance RIN | REFERENCE INPUT | typ 100 kΩ | 7 |
| Gain to output | REFERENCE INPUT | typ 1 V/V | 7 |
| Reference gain error | REFERENCE INPUT | typ 0.01 % | 7 |
| Quiescent current IQ | VIN = 0 V; TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, G = 1 | typ 200 · max 250 uA | 7 |
| Quiescent current IQ | vs temperature, TA = –40°C to +125°C | typ 250 · max 300 uA | 7 |
Pins, by the datasheet
8- 1 –IN
- Negative (inverting) input. · p. 4
- 2 RG
- Gain setting pin. Place a gain resistor between pin 2 and pin 3. · p. 4
- 3 RG
- Gain setting pin. Place a gain resistor between pin 2 and pin 3. · p. 4
- 4 +IN
- Positive (noninverting) input. · p. 4
- 5 –VS
- Negative supply. · p. 4
- 6 REF
- Reference input; must be driven by low impedance. · p. 4
- 7 VOUT
- Output. · p. 4
- 8 +VS
- Positive supply. · p. 4
Open-source boards using it
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Questions
Is there a KiCad symbol and footprint for the INA826AID?
Yes. The symbol is Celestial_Opamp:TI INA826 and the footprint Package_SO:SOIC-8_3.9x4.9mm_P1.27mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the INA826AID?
SOIC-8, with 8 pins. Its footprint is drawn on this page.
Where is the INA826AID datasheet?
Texas Instruments publishes it: the Datasheet link on this page opens it.
Where can I order the INA826AID?
JLCPCB lists it as part C38433, with 9,032 in stock; the sellers' links on this page open their listings.
What can replace the INA826AID?
Parts like it in the library: the INA821ID by Texas Instruments, the INA849D by Texas Instruments, the INA828ID by Texas Instruments and the AD8421BRZ-R7 by Analog Devices. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the INA826AID?
4 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.