DRV8701PRGE

Q: Is there a KiCad symbol and footprint for the DRV8701PRGE?

Yes. The symbol is EasyEDA_Cloud:DRV8701PRGER and the footprint EasyEDA_Cloud:VQFN-24_L4.0-W4.0-P0.50-BL-EP2.8, both drawn on this page. PCBKit places them on a board for you when you design with it.

Q: What package is the DRV8701PRGE?

VQFN-24-EP(4x4), with 25 pins. Its footprint is drawn on this page.

Q: Where is the DRV8701PRGE datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Q: Where can I order the DRV8701PRGE?

JLCPCB lists it as part C114178, with 2,235 in stock; the sellers' links on this page open their listings.

Q: Which open-source boards use the DRV8701PRGE?

7 boards in 4 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

Texas Instruments

-40℃~+125℃ 1.5V 150mA 300mA 4 5.9V~45V 6mA 800mV Full-Bridge MOSFET Under Voltage Protection、Over Current Protection、Overtemperature protection (OTP) VQFN-24-EP(4x4) Gate Drivers ROHS

Extended

Datasheetti/DRV8701PRGE

Category: Brushed DC Motor Drivers
Package: VQFN-24-EP(4x4)
Pins: 25

Overview

The DRV8701PRGE is a brushed DC Motor Driver made by Texas Instruments in a VQFN-24-EP(4x4) package with 25 pins. -40℃~+125℃ 1.5V 150mA 300mA 4 5.9V~45V 6mA 800mV Full-Bridge MOSFET Under Voltage Protection、Over Current Protection、Overtemperature protection (OTP) VQFN-24-EP(4x4) Gate Drivers ROHS.

PCBKit's library has its KiCad symbol (EasyEDA_Cloud:DRV8701PRGER, from EasyEDA) and its footprint (EasyEDA_Cloud:VQFN-24_L4.0-W4.0-P0.50-BL-EP2.8, from EasyEDA), ready for a KiCad board. 2,235 are in stock at JLCPCB (part C114178). 7 open-source boards in 4 repositories on GitHub use it.

Symbol

EasyEDA_Cloud:DRV8701PRGERFrom EasyEDA

Footprint

EasyEDA_Cloud:VQFN-24_L4.0-W4.0-P0.50-BL-EP2.8From EasyEDA

From the datasheet

Supply, least: 5.9 V · VM, recommended operating min · p. 5
Supply, most: 45 V · VM, recommended operating max · p. 5
Supply, absolute maximum: 47 V · VM, absolute maximum · p. 5
Works from: -40 °C · Operating ambient temperature min · p. 5
Works up to: 125 °C · Operating ambient temperature max · p. 5
Junction, hottest: 150 °C · Operating junction temperature max · p. 5
Takes working: 6 mA · VM operating supply current typical, VM = 24 V; nSLEEP high · p. 7
Takes at most: 9.5 mA · VM operating supply current max, VM = 24 V; nSLEEP high · p. 7
Takes asleep: 9 µA · VM sleep supply current typical, VM = 24 V; nSLEEP = 0; TA = 25°C · p. 7
A pin gives at most: 10 mA · nFAULT, SNSOUT open-drain output current max · p. 5
A pin gives at most: 250 mA · GH1, GL1, GH2, GL2 gate source current absolute max · p. 5
A pin gives at most: 500 mA · GH1, GL1, GH2, GL2 gate sink current absolute max · p. 5
A pin gives at most: 5 mA · SO output current absolute max · p. 5
Junction to air (RGE (VQFN)): 34.8 K/W · Junction-to-ambient thermal resistance · p. 6
Junction to board (RGE (VQFN)): 12.2 K/W · Junction-to-board thermal resistance · p. 6
Junction to case (RGE (VQFN)): 37.1 K/W · Junction-to-case (top) thermal resistance · p. 6

What it is and has

Gate driver: Single H-bridge · p. 1
External MOSFETs: Four N-channel MOSFETs · p. 1
PWM duty cycle: Supports 100% · p. 1
Control interface: PWM (DRV8701P) · p. 1
Gate drive adjustment: 5 levels · p. 1
Logic input compatibility: 1.8 V, 3.3 V, 5 V · p. 1
Current shunt amplifier: 20 V/V · p. 1
Current regulation: Integrated PWM current regulation · p. 1
AVDD regulator: 4.8 V, up to 30 mA · p. 1
DVDD regulator: 3.3 V, up to 30 mA · p. 1
Package: 24-pin VQFN (PowerPAD) · p. 1
Protection: Charge pump undervoltage · p. 1
Protection: Overcurrent protection · p. 1
Protection: Pre-driver fault · p. 1
Protection: Thermal shutdown · p. 1
Gate driver: Single H-bridge, four external N-channel MOSFETs · p. 1
Sleep mode: Enabled using nSLEEP · p. 12
Protection: UVLO, OCP, pre-driver faults, thermal shutdown · p. 12
Integrated LDO outputs: AVDD 4.8 V nominal, DVDD 3.3 V nominal · p. 22

Around it

cap 0.1-µF: between VM and GND; CVM1; ceramic, rated for VM. · p. 4
cap ≥10-µF: between VM and GND; CVM2; rated for VM; additional capacitance may be required based on drive current. · p. 4
cap 1-µF: between VCP and VM; CVCP; 16-V ceramic. · p. 4
cap 0.1-µF: between CPH and CPL; CSW; X7R, rated for VM. · p. 4
cap 1-µF: between DVDD and GND; CDVDD; 6.3-V ceramic. · p. 4
cap 1-µF: between AVDD and GND; CAVDD; 6.3-V ceramic. · p. 4
res See Typical Applications for resistor sizing: between IDRIVE and GND; RIDRIVE; sets gate drive current. · p. 4
res ≥10-kΩ: between VCC and nFAULT; RnFAULT pullup; VCC may be the controller supply, AVDD, or DVDD. · p. 4
res ≥10-kΩ: between VCC and SNSOUT; RSNSOUT pullup; VCC may be the controller supply, AVDD, or DVDD. · p. 4
res Unspecified: between SP and SN/GND; RSENSE; optional low-side sense resistor. · p. 4
res 33 kΩ: between IDRIVE and GND; Example setting for 12.5-mA source and 25-mA sink gate drive. · p. 29
res 50 mΩ: between SP and SN; Example sense resistor for a desired chopping current of 3 A. · p. 29
res 2 kΩ: between AVDD and VREF; R1 in the example divider setting VREF to approximately 3 V. · p. 29
res 3.3 kΩ: between VREF and GND; R2 in the example divider setting VREF to approximately 3 V. · p. 29

Specifications

105

Parameter	Conditions	As printed	Page
Power supply voltage (VM)	Referenced to GND; over operating free-air temperature range	min -0.3 · max 47 V	5
Power supply voltage ramp rate (VM)		min 0 · max 2 V/us	5
Charge pump voltage (VCP, CPH)	Maximum is VM + 12 V	min -0.3 V	5
Charge pump negative switching pin (CPL)	Maximum is VM	min -0.3 V	5
Internal logic regulator voltage (DVDD)		min -0.3 · max 3.8 V	5
Internal analog regulator voltage (AVDD)		min -0.3 · max 5.75 V	5
Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT)		min -0.3 · max 5.75 V	5
High-side gate pin voltage (GH1, GH2)	Maximum is VM + 12 V	min -0.3 V	5
Continuous phase node pin voltage (SH1, SH2)	Maximum is VM + 1.2 V	min -1.2 V	5
Pulsed 10 us phase node pin voltage (SH1, SH2)	Maximum is VM + 2 V	min -2 V	5
Low-side gate pin voltage (GL1, GL2)		min -0.3 · max 12 V	5
Continuous shunt amplifier input pin voltage (SP, SN)		min -0.5 · max 1 V	5
Pulsed 10-us shunt amplifier input pin voltage (SP, SN)		min -1 · max 1 V	5
Shunt amplifier output pin voltage (SO)		min -0.3 · max 5.75 V	5
Open-drain output current (nFAULT, SNSOUT)		min 0 · max 10 mA	5
Gate pin source current (GH1, GL1, GH2, GL2)		min 0 · max 250 mA	5
Gate pin sink current (GH1, GL1, GH2, GL2)		min 0 · max 500 mA	5
Shunt amplifier output pin current (SO)		min 0 · max 5 mA	5
Operating junction temperature TJ		min -40 · max 150 °C	5
Storage temperature Tstg		min -65 · max 150 °C	5
Electrostatic discharge V(ESD)	Human body model (HBM) ESD stress voltage; rating ±2000 V	max 2000 V	5
Electrostatic discharge V(ESD)	Charged device model (CDM) ESD stress voltage; rating ±500 V	max 500 V	5
Power supply voltage range VM	Over operating free-air temperature range	min 5.9 · max 45 V	5
Logic level input voltage VCC		min 0 · max 5.5 V	5
Reference RMS voltage range (VREF) VREF	Maximum is AVDD; operational below 0.3 V with degraded accuracy	min 0.3 V	5
Applied PWM signal (PH/EN or IN1/IN2) ƒPWM		max 100 kHz	5
AVDD external load current IAVDD	Power dissipation and thermal limits must be observed	max 30 mA	5
DVDD external load current IDVDD	Power dissipation and thermal limits must be observed	max 30 mA	5
Shunt amplifier output current loading (SO) ISO		max 5 mA	5
Operating ambient temperature TA		min -40 · max 125 °C	5
Junction-to-ambient thermal resistance RθJA	DRV8701; RGE (VQFN); 24 PINS	typ 34.8 °C/W	6
Junction-to-case (top) thermal resistance RθJC(top)	DRV8701; RGE (VQFN); 24 PINS	typ 37.1 °C/W	6
Junction-to-board thermal resistance RθJB	DRV8701; RGE (VQFN); 24 PINS	typ 12.2 °C/W	6
Junction-to-top characterization parameter ψJT	DRV8701; RGE (VQFN); 24 PINS	typ 0.6 °C/W	6
Junction-to-board characterization parameter ψJB	DRV8701; RGE (VQFN); 24 PINS	typ 12.2 °C/W	6
Junction-to-case (bottom) thermal resistance RθJC(bot)	DRV8701; RGE (VQFN); 24 PINS	typ 3.7 °C/W	6
VM operating voltage VM	Over operating free-air temperature range	min 5.9 · max 45 V	7
VM operating supply current IVM	VM = 24 V; nSLEEP high	typ 6 · max 9.5 mA	7
VM sleep mode supply current IVMQ	nSLEEP = 0; VM = 24 V; TA = 25°C	typ 9 · max 15 uA	7
VM sleep mode supply current IVMQ	nSLEEP = 0; VM = 24 V; TA = 125°C; specified by design and characterization data	typ 14 · max 25 uA	7
Sleep time tSLEEP	nSLEEP low to sleep mode	max 100 us	7
Wake-up time tWAKE	nSLEEP high to output change	max 1 ms	7
Turn-on time tON	VM > UVLO to output transition	max 1 ms	7
Internal logic regulator voltage DVDD	External load 0 to 30 mA	min 3 · typ 3.3 · max 3.5 V	7
Internal logic regulator voltage AVDD	External load 0 to 30 mA	min 4.4 · typ 4.8 · max 5.2 V	7
VCP operating voltage VCP	VM = 12 V; IVCP = 0 to 12 mA	min 20.5 · typ 21.5 · max 22.5 V	7
VCP operating voltage VCP	VM = 8 V; IVCP = 0 to 10 mA	min 13.5 · typ 14.4 · max 15 V	7
VCP operating voltage VCP	VM = 5.9 V; IVCP = 0 to 8 mA	min 9.4 · typ 9.9 · max 10.4 V	7
Charge pump current capacity IVCP	VM > 12 V	min 12 mA	7
Charge pump current capacity IVCP	8 V < VM < 12 V	min 10 mA	7
Charge pump current capacity IVCP	5.9 V < VM < 8 V	min 8 mA	7
Charge pump switching frequency fVCP	VM > UVLO; specified by design and characterization data	min 200 · typ 400 · max 700 kHz	7
Input logic low voltage VIL	IN1, IN2, nSLEEP	max 0.8 V	7
Input logic high voltage VIH	IN1, IN2, nSLEEP	min 1.5 V	7
Input logic hysteresis VHYS	IN1, IN2, nSLEEP	min 100 mV	7
Input logic low current IIL	VIN = 0 V	min -5 · max 5 uA	7
Input logic high current IIH	VIN = 5 V	max 78 uA	7
Pulldown resistance RPD	IN1, IN2, nSLEEP	min 64 · typ 115 · max 173 kΩ	7
Propagation delay tPD	IN1/IN2 to GHx/GLx	typ 500 ns	7
Output logic low voltage VOL	nFAULT, SNSOUT; IO = 2 mA	max 0.1 V	7
Output high impedance leakage IOZ	nFAULT, SNSOUT; VIN = 5 V	min -2 · max 2 uA	7
High-side VGS gate drive (gate-to-source) VGHS	VM > 12 V; VGHS with respect to SHx	min 8.5 · typ 9.5 · max 10.5 V	7
High-side VGS gate drive (gate-to-source) VGHS	VM = 8 V; VGHS with respect to SHx	min 5.5 · typ 6.4 · max 7 V	7
High-side VGS gate drive (gate-to-source) VGHS	VM = 5.9 V; VGHS with respect to SHx	min 3.5 · typ 4 · max 4.5 V	7
Low-side VGS gate drive (gate-to-source) VGLS	VM > 12 V	min 8.5 · typ 9.3 · max 10.5 V	7
Low-side VGS gate drive (gate-to-source) VGLS	VM = 5.9 V	min 3.9 · typ 4.3 · max 4.9 V	7
Output dead time tDEAD	Observed tDEAD depends on IDRIVE setting	typ 380 ns	7
Gate drive time tDRIVE		typ 2.5 us	7
Peak source current IDRIVE,SRC	RIDRIVE < 1 kΩ to GND	typ 6 mA	7
Peak source current IDRIVE,SRC	RIDRIVE = 33 kΩ ±5% to GND	typ 12.5 mA	7
Peak source current IDRIVE,SRC	RIDRIVE = 200 kΩ ±5% to GND, or RIDRIVE < 1 kΩ to AVDD	typ 25 mA	7
Peak source current IDRIVE,SRC	RIDRIVE > 500 kΩ ±5% to GND	typ 100 mA	7
Peak source current IDRIVE,SRC	RIDRIVE = 68 kΩ ±5% to AVDD	typ 150 mA	7
Peak sink current IDRIVE,SNK	RIDRIVE < 1 kΩ to GND	typ 12.5 mA	8
Peak sink current IDRIVE,SNK	RIDRIVE = 33 kΩ ±5% to GND	typ 25 mA	8
Peak sink current IDRIVE,SNK	RIDRIVE = 200 kΩ ±5% to GND, or RIDRIVE < 1 kΩ to AVDD	typ 50 mA	8
Peak sink current IDRIVE,SNK	RIDRIVE > 500 ±5% kΩ to GND	typ 200 mA	8
Peak sink current IDRIVE,SNK	RIDRIVE = 68 kΩ ±5% to AVDD	typ 300 mA	8
FET holding current IHOLD	Source current after tDRIVE	typ 6 mA	8
FET holding current IHOLD	Sink current after tDRIVE	typ 25 mA	8
FET hold-off strong pulldown ISTRONG	GHx	typ 490 mA	8
FET hold-off strong pulldown ISTRONG	GLx	typ 690 mA	8
FET gate hold-off resistor ROFF	Pulldown GHx to SHx	typ 200 kΩ	8
FET gate hold-off resistor ROFF	Pulldown GLx to GND	typ 150 kΩ	8
VREF input voltage VVREF	For current internal chopping; maximum is AVDD; operational below 0.3 V with degraded accuracy	min 0.3 V	8
Amplifier gain AV	50 < VSP < 200 mV; VSN = GND	min 18 · typ 20 · max 22 V/V	8
Amplifier gain AV	10 < VSP < 50 mV; VSN = GND	min 16 · typ 20 · max 24 V/V	8
SO offset VOFF	VSP = VSN = GND	typ 50 · max 250 mV	8
SP input current ISP	VSP = 100 mV; VSN = GND	typ -40 uA	8
Settling time to ±1% tSET	VSP = VSN = GND to VSP = 100 mV, VSN = GND; specified by design and characterization data	max 1.5 us	8
Allowable SO pin capacitance CSO	Specified by design and characterization data	max 1 nF	8
PWM current regulation off-time tOFF		typ 25 us	8
PWM blanking time tBLANK		typ 2 us	8
VM undervoltage lockout VUVLO	VM falling; UVLO report	typ 5.4 · max 5.8 V	8
VM undervoltage lockout VUVLO	VM rising; UVLO recovery	typ 5.6 · max 5.9 V	8
VM undervoltage hysteresis VUVLO,HYS	Rising to falling threshold	min 100 mV	8
VM UVLO falling deglitch time tUVLO	VM falling; UVLO report	typ 10 us	8
Overcurrent protection trip level, VDS of each external FET VDS OCP	High-side FETs: VM – SHx; Low-side FETs: SHx – SP	min 0.8 · typ 1 V	8
Overcurrent protection trip level, measured by sense amplifier VSP OCP	VSP voltage with respect to GND	min 0.8 · typ 1 V	8
Overcurrent deglitch time tOCP		typ 4.5 us	8
Overcurrent retry time tRETRY		typ 3 ms	8
Thermal shutdown temperature TTSD	Die temperature, TJ; specified by design and characterization data	min 150 °C	8
Thermal shutdown hysteresis THYS	Die temperature, TJ; specified by design and characterization data	typ 20 °C	8
Gate drive clamping voltage VGS CLAMP	Positive clamping voltage	min 10.5 · max 13 V	8
Gate drive clamping voltage VGS CLAMP	Negative clamping voltage	min -1 · typ -0.7 · max -0.5 V	8

Pins, by the datasheet

1 VM: Motor supply; bypass to GND with 0.1-uF ceramic plus at least 10-uF capacitance rated for VM. · p. 3
2 VCP: Charge pump output; connect a 16-V, 1-uF ceramic capacitor to VM. · p. 3
3 CPH: Charge pump switching node; connect a 0.1-uF X7R capacitor rated for VM between CPH and CPL. · p. 3
4 CPL: Charge pump switching node; connect a 0.1-uF X7R capacitor rated for VM between CPH and CPL. · p. 3
5 GND: Device ground; must be connected to ground. · p. 3
6 VREF: Analog reference input controlling current regulation; apply a voltage between 0.3 V and AVDD. · p. 4
7 AVDD: 4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-uF ceramic capacitor. · p. 3
8 DVDD: 3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-uF ceramic capacitor. · p. 3
9 nFAULT: Pulled low with a fault condition; requires an external pullup. · p. 4
10 SNSOUT: Pulled low when drive current reaches the current chopping threshold; requires an external pullup. · p. 4
11 SO: Shunt amplifier output equals SP voltage times AV plus an offset; connect no more than 1 nF capacitance. · p. 4
12 IDRIVE: Resistor value or forced voltage sets gate drive current. · p. 3
13 nSLEEP: Pull low for low-power sleep with FETs High-Z; internal pulldown. · p. 3
14 IN2: Bridge PWM input; logic controls the state of the H-bridge. · p. 3
15 IN1: Bridge PWM input; logic controls the state of the H-bridge. · p. 3
16 GND: Device ground; must be connected to ground. · p. 3
17 GH1: High-side gate drive; connect to high-side FET gate. · p. 4
18 SH1: Phase node; connect to high-side FET source and low-side FET drain. · p. 4
19 GL1: Low-side gate drive; connect to low-side FET gate. · p. 4
20 SN: Shunt amplifier negative input; connect to SP through current sense resistor and to GND. · p. 4
21 SP: Shunt amplifier positive input; connect to low-side FET source and to SN through current sense resistor. · p. 4
22 GL2: Low-side gate drive; connect to low-side FET gate. · p. 4
23 SH2: Phase node; connect to high-side FET source and low-side FET drain. · p. 4
24 GH2: High-side gate drive; connect to high-side FET gate. · p. 4
PPAD GND: Device ground; must be connected to ground. · p. 3

Ordering codes, by the datasheet

DRV8701PRGER: VQFN (RGE), 24 pins · PWM interface; active; 3000-piece large tape and reel; operating temperature -40 to 125 °C · p. 35
DRV8701PRGER.A: VQFN (RGE), 24 pins · PWM interface; active; 3000-piece large tape and reel; operating temperature -40 to 125 °C · p. 35
DRV8701PRGET: VQFN (RGE), 24 pins · PWM interface; obsolete; operating temperature -40 to 125 °C · p. 35

Parameters

Current - Output High(IOH): 150mA
Current - Output Low(IOL): 300mA
Current - Supply: 6mA
Current - Supply(Max): 9.5mA
Driven Configuration: Full Bridge
Features: Enable shutdown
Input Logic Level - High: 1.5V
Input Logic Level - Low: 800mV
Interface: PWM
Junction Temperature(Max): 150℃
Load Type: MOSFET
Number of Drivers: 4
Number of H-bridges: 1
Operating Temperature: -40℃~+125℃
Output Current per Pin(Max): 10mA
Quiescent Current(Iq): 6mA
Standby Current: 9uA
Technology: No
Thermal Resistance(Junction to Ambient): 34.8℃/W
Thermal Resistance(Junction to Board): 12.2℃/W
Thermal Resistance(Junction to Case): 37.1℃/W
Voltage - Supply: 5.9V~45V
Voltage - Supply(Absolute Max): 47V

Order codes

DRV8701PRGERLCSC C114178
DRV8701PRGETLCSC C2150478

Pinout

The pins of the DRV8701PRGE
Pin	Name	Type
1	VM	Unspecified
2	VCP	Unspecified
3	CPH	Unspecified
4	CPL	Unspecified
5	GND	Unspecified
6	VREF	Unspecified
7	AVDD	Unspecified
8	DVDD	Unspecified
9	nFAULT	Unspecified
10	SNSOUT	Unspecified
11	SO	Unspecified
12	IDRIVE	Unspecified
13	nSLEEP	Unspecified
14	IN2	Unspecified
15	IN1	Unspecified
16	GND	Unspecified
17	GH1	Unspecified
18	SH1	Unspecified
19	GL1	Unspecified
20	SN	Unspecified
21	SP	Unspecified
22	GL2	Unspecified
23	SH2	Unspecified
24	GH2	Unspecified
25	GND	Unspecified

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Questions

Is there a KiCad symbol and footprint for the DRV8701PRGE?

Yes. The symbol is EasyEDA_Cloud:DRV8701PRGER and the footprint EasyEDA_Cloud:VQFN-24_L4.0-W4.0-P0.50-BL-EP2.8, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the DRV8701PRGE?