ADS1220IPW

Texas InstrumentsExtended

-40℃~+125℃ 100nA 2.3V~5.5V 24 2kHz 2、4 500kHz~4.5MHz、4.096MHz 6LSB Built-in Built-in Built-in temperature sensor、Multiplexers、Integrated modulator SPI Sigma-Delta Support Yes TSSOP-16 Analog to Digital Converters (ADC) ROHS

Datasheet JLCPCB LCSC

Part id: ti/ADS1220IPW
Category: Analog To Digital Converters (ADC)
Package: TSSOP-16
Pins: 16
In stock: 17,235 at JLCPCB (C48263)
Used on: 7 open-source boards

Overview

The ADS1220IPW is an analog To Digital Converter made by Texas Instruments in a TSSOP-16 package with 16 pins. -40℃~+125℃ 100nA 2.3V~5.5V 24 2kHz 2、4 500kHz~4.5MHz、4.096MHz 6LSB Built-in Built-in Built-in temperature sensor、Multiplexers、Integrated modulator SPI Sigma-Delta Support Yes TSSOP-16 Analog to Digital Converters (ADC) ROHS.

PCBKit's library has its KiCad symbol (Analog_ADC:ADS1220xPW, from KiCad's library) and its footprint (Package_SO:TSSOP-16_4.4x5mm_P0.65mm, from KiCad's library), ready for a KiCad board. 17,235 are in stock at JLCPCB (part C48263). 7 open-source boards in 6 repositories on GitHub use it.

Symbol

Analog_ADC:ADS1220xPWFrom KiCad's library

Footprint

Package_SO:TSSOP-16_4.4x5mm_P0.65mmFrom KiCad's library

From the datasheet

Supply, least: 2.3 V · AVDD to AVSS, unipolar recommended operating min · p. 6
Supply, most: 5.5 V · AVDD to AVSS, unipolar recommended operating max · p. 6
Supply, most: 2.75 V · AVDD to DGND, bipolar recommended operating max · p. 6
Supply, least: 2.75 V · AVSS to DGND, bipolar recommended operating min · p. 6
Supply, most: 2.3 V · AVSS to DGND, bipolar recommended operating max · p. 6
Supply, absolute maximum: 7 V · AVDD to AVSS, absolute max · p. 5
Works from: -40 °C · Operating ambient temperature min · p. 6
Works up to: 125 °C · Operating ambient temperature max · p. 6
Junction, hottest: 150 °C · Junction temperature absolute max · p. 5
Takes working: 415 µA · sum of AVDD and DVDD typical, normal mode, gain 1 to 16, internal reference, IDACs off · p. 8
Takes at most: 985 µA · sum of AVDD and DVDD typical, turbo mode, gain 64 or 128, internal reference, IDACs off · p. 8
Takes asleep: 400 nA · sum of AVDD and DVDD typical, power-down mode · p. 8
Junction to air (TSSOP (PW)): 99.5 K/W · Junction-to-ambient thermal resistance · p. 6
Junction to case (TSSOP (PW)): 35.2 K/W · Junction-to-case top thermal resistance · p. 6
Junction to board (TSSOP (PW)): 44.3 K/W · Junction-to-board thermal resistance · p. 6

What it is and has

ADC: 4-channel, 24-bit, up to 2kSPS, integrated PGA and reference · p. 1
Programmable gain: 1 to 128 · p. 1
Effective resolution: Up to 20 Bits · p. 1
Analog inputs: Two differential or four single-ended · p. 1
Excitation current sources: Dual-matched, programmable · p. 1
Internal reference: 2.048V, 5ppm/°C typical drift · p. 1
Internal oscillator: 2% accurate · p. 1
SPI: SPI-compatible interface, mode 1 · p. 1

Around it

cap 100nF (or larger): between AVDD and AVSS; Analog supply decoupling. · p. 4
cap 100nF (or larger): between DVDD and DGND; Digital supply decoupling. · p. 4

Specifications

Parameter	Conditions	As printed	Page
Power-supply voltage	AVDD to AVSS	min -0.3 · max 7 V	5
Power-supply voltage	DVDD to DGND	min -0.3 · max 7 V	5
Power-supply voltage	AVSS to DGND	min -2.8 · max 0.3 V	5
Input current	Continuous, any pin except power supply pins	min -10 · max 10 mA	5
Temperature TJ	Junction	min -40 · max 150 °C	5
Temperature Tstg	Storage	min -60 · max 150 °C	5
Electrostatic discharge V(ESD)	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	min -2000 · max 2000 V	5
Electrostatic discharge V(ESD)	Charged-device model (CDM), per JEDEC specification JESD22C101	min -500 · max 500 V	5
Unipolar analog power supply	AVDD to AVSS	min 2.3 · max 5.5 V	6
Unipolar analog power supply	AVSS to DGND; nominal 0 V	min -0.1 · typ 0 · max 0.1 V	6
Bipolar analog power supply	AVDD to DGND; nominal 2.5 V	min 2.3 · typ 2.5 · max 2.75 V	6
Bipolar analog power supply	AVSS to DGND; nominal –2.5 V	min -2.75 · typ -2.5 · max -2.3 V	6
Digital power supply	DVDD to DGND	min 2.3 · max 5.5 V	6
Differential reference input voltage VREF	VREF = VREFPx – VREFNx; nominal 2.5 V; maximum AVDD – AVSS	min 0.75 · typ 2.5 V	6
External clock frequency fCLK	Nominal 4.096 MHz	min 0.5 · typ 4.096 · max 4.5 MHz	6
Duty cycle	External clock source	min 40 · max 60 %	6
Operating ambient temperature TA		min -40 · max 125 °C	6
Junction-to-ambient thermal resistance RθJA	TSSOP (PW), 16 pins	typ 99.5 °C/W	6
Junction-to-case (top) thermal resistance RθJC(top)	TSSOP (PW), 16 pins	typ 35.2 °C/W	6
Junction-to-board thermal resistance RθJB	TSSOP (PW), 16 pins	typ 44.3 °C/W	6
Junction-to-top characterization parameter ψJT	TSSOP (PW), 16 pins	typ 2.4 °C/W	6
Junction-to-board characterization parameter ψJB	TSSOP (PW), 16 pins	typ 43.8 °C/W	6
Resolution (no missing codes)		min 24 Bits	7
Integral nonlinearity INL	Gain = 1 to 128, VCM = 0.5 AVDD, best fit; typical ±6	min -15 · typ 6 · max 15 ppmFSR	7
Input offset voltage VIO	PGA disabled, gain = 1 to 4, differential inputs; typical ±4	typ 4 uV	7
Input offset voltage VIO	Gain = 1, differential inputs, TA = 25°C; typical ±4	min -30 · typ 4 · max 30 uV	7
Input offset voltage VIO	Gain = 2 to 128, differential inputs; typical ±4	typ 4 uV	7
Offset drift	PGA disabled, gain = 1 to 4	typ 0.25 uV/°C	7
Offset drift	Gain = 1 to 128, TA = –40°C to +85°C	typ 0.08 · max 0.3 uV/°C	7
Offset drift	Gain = 1 to 128	typ 0.25 uV/°C	7
Offset match	Match between any two inputs; typical ±20	typ 20 uV	7
Gain error	PGA disabled, gain = 1 to 4; typical ±0.015%	typ 0.015 %	7
Gain error	Gain = 1 to 128, TA = 25°C; typical ±0.015%	min -0.1 · typ 0.015 · max 0.1 %	7
Gain drift	PGA disabled, gain = 1 to 4	typ 1 ppm/°C	7
Gain drift	Gain = 1 to 128	typ 1 · max 4 ppm/°C	7
Normal-mode rejection ratio NMRR	50Hz ±3%, DR = 20SPS, external CLK, 50/60 bit = 10b	min 105 dB	7
Normal-mode rejection ratio NMRR	60Hz ±3%, DR = 20SPS, external CLK, 50/60 bit = 11b	min 105 dB	7
Normal-mode rejection ratio NMRR	50Hz or 60Hz ±3%, DR = 20SPS, external CLK, 50/60 bit = 01b	min 90 dB	7
Common-mode rejection ratio CMRR	At dc, gain = 1	min 90 · typ 105 dB	7
Common-mode rejection ratio CMRR	fCM = 50Hz, DR = 2000SPS	min 95 · typ 115 dB	7
Common-mode rejection ratio CMRR	fCM = 60Hz, DR = 2000SPS	min 95 · typ 115 dB	7
Power-supply rejection ratio PSRR	AVDD at dc, VCM = 0.5 AVDD, gain = 1	min 80 · typ 105 dB	7
Power-supply rejection ratio PSRR	DVDD at dc, VCM = 0.5 AVDD, gain = 1	min 100 · typ 115 dB	7
Initial accuracy	Internal voltage reference; TA = 25°C	min 2.045 · typ 2.048 · max 2.051 V	7
Reference drift	Internal voltage reference	typ 5 · max 30 ppm/°C	7
Long-term drift	Internal voltage reference; 1000 hours	typ 110 ppm	7
Reference input current	REFP0 = VREF, REFN0 = AVSS; typical ±10	typ 10 nA	7
Internal oscillator accuracy	Normal mode; typical ±1%	min -2 · typ 1 · max 2 %	7
Accuracy	All current settings, each IDAC; typical ±1%	min -6 · typ 1 · max 6 %	7
Current match	Between IDACs (not valid for 10uA setting); typical ±0.3%	typ 0.3 %	7
Temperature drift	Each IDAC (not valid for 10uA setting)	typ 50 ppm/°C	7
Temperature drift matching	Between IDACs (not valid for 10uA setting)	typ 10 ppm/°C	7
Conversion resolution	Temperature sensor	typ 14 Bits	8
Temperature resolution	Temperature sensor	typ 0.03125 °C	8
Accuracy	Temperature sensor; TA = 0°C to +75°C; typical ±0.25	min -0.5 · typ 0.25 · max 0.5 °C	8
Accuracy	Temperature sensor; TA = –40°C to +125°C; typical ±0.5	min -1 · typ 0.5 · max 1 °C	8
Accuracy vs analog supply voltage	Temperature sensor	typ 0.0625 · max 0.25 °C/V	8
On-resistance RON	Low-side power switch	typ 3.5 · max 5.5 Ω	8
Current through switch	Low-side power switch	max 30 mA	8
Input leakage, high IH	VIH = 5.5V	min -10 · max 10 uA	8
Input leakage, low IL	VIL = DGND	min -10 · max 10 uA	8
Analog supply current IAVDD	Power-down mode	typ 0.1 · max 3 uA	8
Analog supply current IAVDD	Duty-cycle mode, PGA disabled	typ 65 uA	8
Analog supply current IAVDD	Duty-cycle mode, gain = 1 to 16	typ 95 uA	8
Analog supply current IAVDD	Duty-cycle mode, gain = 32	typ 115 uA	8
Analog supply current IAVDD	Duty-cycle mode, gain = 64, 128	typ 135 uA	8
Analog supply current IAVDD	Normal mode, PGA disabled	typ 240 uA	8
Analog supply current IAVDD	Normal mode, gain = 1 to 16	typ 340 · max 490 uA	8
Analog supply current IAVDD	Normal mode, gain = 32	typ 425 uA	8
Analog supply current IAVDD	Normal mode, gain = 64, 128	typ 510 uA	8
Analog supply current IAVDD	Turbo mode, PGA disabled	typ 360 uA	8
Analog supply current IAVDD	Turbo mode, gain = 1 to 16	typ 540 uA	8
Analog supply current IAVDD	Turbo mode, gain = 32	typ 715 uA	8
Analog supply current IAVDD	Turbo mode, gain = 64, 128	typ 890 uA	8
Digital supply current IDVDD	Power-down mode	typ 0.3 · max 5 uA	8
Digital supply current IDVDD	Duty-cycle mode	typ 55 uA	8
Digital supply current IDVDD	Normal mode	typ 75 · max 110 uA	8
Digital supply current IDVDD	Turbo mode	typ 95 uA	8
Power dissipation PD	Duty-cycle mode, PGA disabled	typ 0.4 mW	8
Power dissipation PD	Normal mode, gain = 1 to 16	typ 1.4 mW	8
Power dissipation PD	Turbo mode, gain = 1 to 16	typ 2.1 mW	8
Delay time, CS falling edge to first SCLK rising edge td(CSSC)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 50 ns	9
Delay time, final SCLK falling edge to CS rising edge td(SCCS)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 25 ns	9
Pulse duration, CS high tw(CSH)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 50 ns	9
SCLK period tc(SC)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 150 ns	9
Pulse duration, SCLK high tw(SCH)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 60 ns	9
Pulse duration, SCLK low tw(SCL)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 60 ns	9
Setup time, DIN valid before SCLK falling edge tsu(DI)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 50 ns	9
Hold time, DIN valid after SCLK falling edge th(DI)	Operating ambient temperature range; DVDD = 2.3V to 5.5V	min 25 ns	9
SPI timeout	Normal mode, duty-cycle mode	max 14000 tMOD	9
SPI timeout	Turbo mode	max 28000 tMOD	9
Propagation delay time, CS falling edge to DOUT driven tp(CSDO)	DOUT load = 20pF \|\| 10kΩ to DGND	max 50 ns	9
Propagation delay time, SCLK rising edge to valid new DOUT tp(SCDO)	DOUT load = 20pF \|\| 10kΩ to DGND	min 0 · max 50 ns	9
Propagation delay time, CS rising edge to DOUT high impedance tp(CSDOZ)	DOUT load = 20pF \|\| 10kΩ to DGND	max 50 ns	9

Pins, by the datasheet

1 SCLK: Serial clock input. · p. 4
2 CS: Chip select, active low; connect to DGND if not used. · p. 4
3 CLK: External clock source pin; connect to DGND if not used. · p. 4
4 DGND: Digital ground. · p. 4
5 AVSS: Negative analog power supply. · p. 4
6 AIN3/REFN1: Analog input 3 and negative reference input 1; internal low-side power switch connects this pin to AVSS. · p. 4
7 AIN2: Analog input 2. · p. 4
8 REFN0: Negative reference input 0. · p. 4
9 REFP0: Positive reference input 0. · p. 4
10 AIN1: Analog input 1. · p. 4
11 AIN0/REFP1: Analog input 0 and positive reference input 1. · p. 4
12 AVDD: Positive analog power supply; connect a 100nF or larger capacitor to AVSS. · p. 4
13 DVDD: Positive digital power supply; connect a 100nF or larger capacitor to DGND. · p. 4
14 DRDY: Data ready, active low; leave unconnected or tie to DVDD with a weak pull-up resistor if unused. · p. 4
15 DOUT/ DRDY: Serial data output combined with data ready, active low. · p. 4
16 DIN: Serial data input. · p. 4

Parameters

ADC architecture: Sigma-Delta
Clock Frequency: 4.096MHz
Clock/Oscillator: Built-in
Current - Supply: 415uA
Current - Supply(Max): 985uA
Features: Built-in temperature sensor
Integral non - linearity: 6LSB
Interface: SPI
Junction Temperature(Max): 150℃
Operating Temperature: -40℃~+125℃
Programmable Gain: Support
Quiescent Current (Iq): 100nA
Resolution (Bits): 24
Sampling Rate: 2kHz
Standby Current: 400nA
Thermal Resistance(Junction to Ambient): 99.5℃/W
Thermal Resistance(Junction to Board): 44.3℃/W
Thermal Resistance(Junction to Case): 35.2℃/W
Voltage - Supply: 2.3V~5.5V
Voltage - Supply(Absolute Max): 7V
Voltage Reference: Built-in
differential input: Yes
number of channels: 2

Order codes

ADS1220IPWLCSC C1542855
ADS1220IPWRLCSC C48263

Pinout

The pins of the ADS1220IPW
Pin	Name	Type
1	SCLK	Input
2	CS	Input
3	CLK	Input
4	DGND	Power in
5	AVSS	Power in
6	AIN3/REFN1	Input
7	AIN2	Input
8	REFN0	Input
9	REFP0	Input
10	AIN1	Input
11	AIN0/REFP1	Input
12	AVDD	Power in
13	DVDD	Power in
14	DRDY	Output
15	DOUT/DRDY	Output
16	DIN	Input

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Parts like it

Questions

Is there a KiCad symbol and footprint for the ADS1220IPW?

Yes. The symbol is Analog_ADC:ADS1220xPW and the footprint Package_SO:TSSOP-16_4.4x5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the ADS1220IPW?

TSSOP-16, with 16 pins. Its footprint is drawn on this page.

Where is the ADS1220IPW datasheet?

Texas Instruments publishes it: the Datasheet link on this page opens it.

Where can I order the ADS1220IPW?

JLCPCB lists it as part C48263, with 17,235 in stock; the sellers' links on this page open their listings.

What can replace the ADS1220IPW?

Parts like it in the library: the ADS1120IPW by Texas Instruments, the ADS1246IPW by Texas Instruments, the SSP1220 by Shanghai Siproin Microelectronics and the ADS1248IPW by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the ADS1220IPW?

7 boards in 6 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

ADS1220IPW

Overview

Symbol

Footprint

From the datasheet

What it is and has

Around it

Specifications

Pins, by the datasheet

Open-source boards using it

Nile amp

Hushlog

LEOS efm

Af pj bis2025

Nestbox

Nestbox

Device

Parts like it

ADS1120IPW

ADS1246IPW

SSP1220

ADS1248IPW

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ADS1220IRVAT