Texas Instruments
-40℃~+125℃ 0.5LSB 12 128Hz、250Hz、490Hz、920Hz、1.6kHz、2.4kHz、3.3kHz 1MHz 2 2V~5.5V 2uA 3.3kHz 5ppm/℃ 6.144V Built-in Built-in I2C Sigma-Delta Support Yes VSSOP-10-0.5mm Analog to Digital Converters (ADC) ROHS
The ADS1015IDGS is an analog To Digital Converter made by Texas Instruments in a VSSOP-10-0.5mm package with 10 pins. -40℃~+125℃ 0.5LSB 12 128Hz、250Hz、490Hz、920Hz、1.6kHz、2.4kHz、3.3kHz 1MHz 2 2V~5.5V 2uA 3.3kHz 5ppm/℃ 6.144V Built-in Built-in I2C Sigma-Delta Support Yes VSSOP-10-0.5mm Analog to Digital Converters (ADC) ROHS.
PCBKit's library has its KiCad symbol (Analog_ADC:ADS1015IDGS, from KiCad's library) and its footprint (Package_SO:TSSOP-10_3x3mm_P0.5mm, from KiCad's library), ready for a KiCad board. 918 are in stock at JLCPCB (part C193969). 52 open-source boards in 44 repositories on GitHub use it.
| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Power-supply voltage | VDD to GND | min -0.3 · max 7 V | 4 |
| Digital input voltage | SDA, SCL, ADDR, ALERT/RDY; minimum GND – 0.3 | max 5.5 V | 4 |
| Input current, continuous | Any pin except power supply pins | min -10 · max 10 mA | 4 |
| Temperature TA | Operating ambient | min -40 · max 125 °C | 4 |
| Temperature TJ | Junction | min -40 · max 150 °C | 4 |
| Temperature Tstg | Storage | min -60 · max 150 °C | 4 |
| Electrostatic discharge V(ESD) | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001; rating ±2000 V | max 2000 V | 4 |
| Electrostatic discharge V(ESD) | Charged-device model (CDM), per JEDEC specification JESD22-C101; rating ±500 V | max 500 V | 4 |
| Power supply (VDD to GND) | min 2 · max 5.5 V | 4 | |
| Full-scale input voltage range FSR | VIN = V(AINP) – V(AINN); selectable bipolar ranges from ±0.256 V to ±6.144 V | min 0.256 · max 6.144 V | 4 |
| Digital input voltage VDIG | Minimum GND | max 5.5 V | 4 |
| Operating ambient temperature TA | min -40 · max 125 °C | 4 | |
| Junction-to-ambient thermal resistance RθJA | DGS (VSSOP), 10 pins | typ 182.7 °C/W | 4 |
| Junction-to-case (top) thermal resistance RθJC(top) | DGS (VSSOP), 10 pins | typ 67.2 °C/W | 4 |
| Junction-to-board thermal resistance RθJB | DGS (VSSOP), 10 pins | typ 103.8 °C/W | 4 |
| Junction-to-top characterization parameter ψJT | DGS (VSSOP), 10 pins | typ 10.2 °C/W | 4 |
| Junction-to-board characterization parameter ψJB | DGS (VSSOP), 10 pins | typ 102.8 °C/W | 4 |
| Common-mode input impedance | FSR = ±6.144V | typ 10 MΩ | 5 |
| Common-mode input impedance | FSR = ±4.096V, FSR = ±2.048V | typ 6 MΩ | 5 |
| Common-mode input impedance | FSR = ±1.024V | typ 3 MΩ | 5 |
| Common-mode input impedance | FSR = ±0.512V, FSR = ±0.256V | typ 100 MΩ | 5 |
| Differential input impedance | FSR = ±6.144V | typ 22 MΩ | 5 |
| Differential input impedance | FSR = ±4.096V | typ 15 MΩ | 5 |
| Differential input impedance | FSR = ±2.048V | typ 4.9 MΩ | 5 |
| Differential input impedance | FSR = ±1.024V | typ 2.4 MΩ | 5 |
| Differential input impedance | FSR = ±0.512V, ±0.256V | typ 710 kΩ | 5 |
| Resolution (no missing codes) | min 12 Bits | 5 | |
| Data rate variation | All data rates | min -10 · max 10 % | 5 |
| Integral nonlinearity INL | DR = 128SPS, FSR = ±2.048V; best-fit INL; covers 99% of full-scale | max 0.5 LSB | 5 |
| Offset error | FSR = ±2.048V, differential inputs | min -0.5 · typ 0 · max 0.5 LSB | 5 |
| Offset error | FSR = ±2.048V, single-ended inputs; typical ±0.25 LSB | typ 0.25 LSB | 5 |
| Offset drift over temperature | FSR = ±2.048V | typ 0.005 LSB/°C | 5 |
| Long-term offset drift | FSR = ±2.048V, TA = 125°C, 1000 hrs; typical ±1 LSB | typ 1 LSB | 5 |
| Offset channel match | Match between any two inputs | typ 0.25 LSB | 5 |
| Gain error | FSR = ±2.048V, TA = 25°C; includes onboard PGA and voltage reference errors | typ 0.05 · max 0.25 % | 5 |
| Gain drift over temperature | FSR = ±0.256V | typ 7 ppm/°C | 5 |
| Gain drift over temperature | FSR = ±2.048V | typ 5 · max 40 ppm/°C | 5 |
| Gain drift over temperature | FSR = ±6.144V | typ 5 ppm/°C | 5 |
| Long-term gain drift | FSR = ±2.048V, TA = 125°C, 1000 hrs; typical ±0.05% | typ 0.05 % | 5 |
| Gain match | Match between any two gains | typ 0.02 · max 0.1 % | 5 |
| Gain channel match | Match between any two inputs | typ 0.05 · max 0.1 % | 5 |
| High-level input voltage VIH | Minimum 0.7 VDD | max 5.5 V | 5 |
| Low-level output voltage VOL | IOL = 3mA; minimum GND | typ 0.15 · max 0.4 V | 5 |
| Input leakage current | GND < VDIG < VDD | min -10 · max 10 uA | 5 |
| Supply current IVDD | Power-down, TA = 25°C; VDD = 3.3V | typ 0.5 · max 2 uA | 6 |
| Supply current IVDD | Operating, TA = 25°C; VDD = 3.3V, data rate = 128SPS, FSR = ±2.048V | typ 150 · max 200 uA | 6 |
| Supply current IVDD | Operating, TA = –40°C to +125°C; VDD = 3.3V, data rate = 128SPS, FSR = ±2.048V | max 300 uA | 6 |
| Power dissipation PD | VDD = 5.0V | typ 0.9 mW | 6 |
| Power dissipation PD | VDD = 3.3V | typ 0.5 mW | 6 |
| Power dissipation PD | VDD = 2.0V | typ 0.3 mW | 6 |
| SCL clock frequency fSCL | FAST MODE; VDD = 2.0V to 5.5V | min 0.01 · max 0.4 MHz | 6 |
| SCL clock frequency fSCL | HIGH-SPEED MODE; VDD = 2.0V to 5.5V | min 0.01 · max 3.4 MHz | 6 |
| Bus free time between START and STOP condition tBUF | FAST MODE | min 600 ns | 6 |
| Bus free time between START and STOP condition tBUF | HIGH-SPEED MODE | min 160 ns | 6 |
| Hold time after repeated START condition. After this period, the first clock is generated. tHDSTA | FAST MODE | min 600 ns | 6 |
| Hold time after repeated START condition. After this period, the first clock is generated. tHDSTA | HIGH-SPEED MODE | min 160 ns | 6 |
| Setup time for a repeated START condition tSUSTA | FAST MODE | min 600 ns | 6 |
| Setup time for a repeated START condition tSUSTA | HIGH-SPEED MODE | min 160 ns | 6 |
| Setup time for STOP condition tSUSTO | FAST MODE | min 600 ns | 6 |
| Setup time for STOP condition tSUSTO | HIGH-SPEED MODE | min 160 ns | 6 |
| Data hold time tHDDAT | FAST MODE | min 0 ns | 6 |
| Data hold time tHDDAT | HIGH-SPEED MODE | min 0 ns | 6 |
| Data setup time tSUDAT | FAST MODE | min 100 ns | 6 |
| Data setup time tSUDAT | HIGH-SPEED MODE | min 10 ns | 6 |
| Low period of the SCL clock pin tLOW | FAST MODE | min 1300 ns | 6 |
| Low period of the SCL clock pin tLOW | HIGH-SPEED MODE | min 160 ns | 6 |
| High period for the SCL clock pin tHIGH | FAST MODE | min 600 ns | 6 |
| High period for the SCL clock pin tHIGH | HIGH-SPEED MODE | min 60 ns | 6 |
| Fall time for both SDA and SCL signals tF | FAST MODE | max 300 ns | 6 |
| Fall time for both SDA and SCL signals tF | HIGH-SPEED MODE; bus capacitive load must not exceed 400pF | max 160 ns | 6 |
| Rise time for both SDA and SCL signals tR | FAST MODE | max 300 ns | 6 |
| Rise time for both SDA and SCL signals tR | HIGH-SPEED MODE; bus capacitive load must not exceed 400pF | max 160 ns | 6 |
| Pin | Name | Type |
|---|---|---|
| 1 | ADDR | Input |
| 2 | ALERT/RDY | Output |
| 3 | GND | Power in |
| 4 | AIN0 | Input |
| 5 | AIN1 | Input |
| 6 | AIN2 | Input |
| 7 | AIN3 | Input |
| 8 | VDD | Power in |
| 9 | SDA | Input/output |
| 10 | SCL | Input |
JunOllyLi/TX_PCB
NOTE: the latest PCB had been manufactured was v2.0. But it had the Gimbal ZH-connector reversed. The schematics and PCB drawing had been updated to v2.1 to fix that. But v2.1 had not been really manufactured yet.
proveskit/solar_boards
The solar panel boards for the PROVES Kit
proveskit/battery_board
The battery and power management board for the PROVES Kit.
Alex-C-EE/Reliable-Temp-Monitor
A CAN Node designed to take temperature measurement from 3 analog-output sensors and control 2x 24V fans
krishchan007/DUT_Interface_board_v0.2
v0.2 of DUT interface board with significant changes in layout, architecture etc.
<iframe src="https://pcbkit.io/embed/parts/ti/ADS1015IDGS" title="ADS1015IDGS in PCBKit" width="100%" height="480" style="border:0;border-radius:12px" allow="fullscreen" loading="lazy"></iframe><img src="https://pcbkit.io/embed/parts/ti/ADS1015IDGS.jpg" alt="ADS1015IDGS" width="1200" height="900">[](https://pcbkit.io/parts/ti/ADS1015IDGS)Yes. The symbol is Analog_ADC:ADS1015IDGS and the footprint Package_SO:TSSOP-10_3x3mm_P0.5mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
VSSOP-10-0.5mm, with 10 pins. Its footprint is drawn on this page.
Texas Instruments publishes it: the Datasheet link on this page opens it.
JLCPCB lists it as part C193969, with 918 in stock; the sellers' links on this page open their listings.
Parts like it in the library: the ADS1115IDGST by Texas Instruments, the ADS1014IDGS by Texas Instruments, the ADS1114IDGSR by Texas Instruments and the ADS1118IDGS by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.
52 boards in 44 repositories on GitHub; the most starred are listed on this page, with their KiCad files.
