
STM8S003F3P6
STMicroelectronicsJLCPCB preferred
-40℃~+85℃ 10bit 128Byte 16 16MHz 1KB 2.95V~5.5V 8 Bit 8KB Built-in FLASH STM8 TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHS
- Part id
- st/STM8S003F3P6
- Category
- Microcontrollers (MCU, MPU, SOC)
- Package
- TSSOP-20
- Pins
- 20
- In stock
- 154,831 at JLCPCB (C52717)
- Used on
- 43 open-source boards
Overview
The STM8S003F3P6 is a microcontroller made by STMicroelectronics in a TSSOP-20 package with 20 pins. -40℃~+85℃ 10bit 128Byte 16 16MHz 1KB 2.95V~5.5V 8 Bit 8KB Built-in FLASH STM8 TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHS.
PCBKit's library has its KiCad symbol (EasyEDA_Pro:STM8S003F3P6, from EasyEDA Pro) and its footprint (Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, from KiCad's library), ready for a KiCad board. 154,831 are in stock at JLCPCB (part C52717). 43 open-source boards in 39 repositories on GitHub use it.
Symbol
Footprint
From the datasheet
13- Supply, least
- 2.95 V · VDD, recommended operating min · p. 49
- Supply, most
- 5.5 V · VDD, recommended operating max · p. 49
- Supply, absolute maximum
- 6.5 V · VDDx - VSS, absolute max · p. 47
- Works from
- -40 °C · Ambient temperature, suffix 6, min · p. 49
- Works up to
- 85 °C · Ambient temperature, suffix 6, max · p. 49
- Junction, hottest
- 105 °C · Junction temperature, suffix 6, operating max · p. 49
- Junction, hottest
- 150 °C · Junction temperature, absolute max · p. 48
- Takes working
- 3.7 mA · VDD = 5 V, Flash execution, HSI 16 MHz, peripherals disabled, typical · p. 51
- Takes at most
- 4.75 mA · VDD = 5 V, Flash execution, external clock 16 MHz, max · p. 51
- Takes asleep
- 6 µA · VDD = 5 V, halt, Flash power-down, typical · p. 55
- A pin gives at most
- 20 mA · I/O sink current, absolute max · p. 48
- Junction to air (TSSOP20 - 4.4 mm)
- 84 K/W · Junction to ambient, 4-layer PCB, natural convection · p. 94
- Takes working
- 4.5 mA · Typical Flash execution, 16 MHz HSE crystal, VDD = 5 V, peripherals disabled · p. 51
What it is and has
23- Core
- 16 MHz advanced STM8, Harvard architecture, 3-stage pipeline · p. 1
- Flash memory
- 8 Kbytes · p. 1
- RAM
- 1 Kbytes · p. 1
- Data EEPROM
- 128 bytes · p. 12
- SPI
- Up to 8 Mbit/s · p. 1
- ADC
- 10-bit, ±1 LSB, up to 5 multiplexed channels · p. 1
- Interrupt controller
- 32 interrupts, nested · p. 1
- General purpose timer
- 16-bit, 3 CAPCOM channels · p. 1
- Basic timer
- 8-bit, 8-bit prescaler · p. 1
- Core
- 16 MHz STM8 8-bit MCU · p. 1
- ADC
- 10-bit · p. 1
- Timers
- 3 · p. 1
- Interfaces
- UART, SPI, I²C · p. 1
- Interrupt controller
- Nested, 32 interrupts · p. 1
- External interrupts
- Up to 27 on 6 vectors · p. 1
- Advanced control timer
- 16-bit, 4 CAPCOM channels, 3 complementary outputs · p. 1
- Basic timer
- 8-bit with 8-bit prescaler · p. 1
- Auto wake-up timer
- Included · p. 1
- Watchdogs
- Window watchdog and independent watchdog · p. 1
- Core
- 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline · p. 1
- Interrupt controller
- Nested interrupt controller with 32 interrupts · p. 1
- External interrupts
- Up to 27 external interrupts on 6 vectors · p. 1
- Auto wake-up timer
- Available · p. 1
Around it
8- cap 470–3300 nF
- between VCAP and VSS; External capacitor for main regulator stabilization; ESR at 1 MHz ≤0.3 Ω and ESL ≤15 nH. · p. 49
- diode Schottky
- between Analog input pin and Ground; Recommended on standard analog pins that may inject negative current. · p. 48
- cap 470 to 3300 nF
- between VCAP and VSS; External capacitor; ESR maximum 0.3 Ω at 1 MHz, ESL maximum 15 nH; account for tolerance, temperature, DC bias and frequency. · p. 49
- diode Schottky diode
- between standard analog input pin and ground; Recommended for standard analog pins that may inject negative current, to preserve ADC accuracy. · p. 48
- crystal 1 to 16 MHz
- between OSCIN and OSCOUT; Crystal or ceramic resonator; place the resonator and load capacitors as close as possible to the oscillator pins. · p. 61
- res 4.7kΩ
- between SDA and VDD; Pull-up in the typical I²C application. · p. 81
- res 100Ω
- between SDA and I2C bus SDA; Series resistor in the typical I²C application. · p. 81
- res 100Ω
- between SCL and I2C bus SCL; Series resistor in the typical I²C application. · p. 81
Specifications
180| Parameter | Conditions | As printed | Page |
|---|---|---|---|
| Supply voltage VDDx - VSS | min -0.3 · max 6.5 V | 47 | |
| Input voltage on true open drain pins VIN | max 6.5 V | 47 | |
| Variations between different power pins |VDDx - VDD| | max 50 mV | 47 | |
| Variations between all the different ground pins |VSSx - VSS| | max 50 mV | 47 | |
| Total current into VDD power lines (source) IVDD | max 100 mA | 47 | |
| Total current out of VSS ground lines (sink) IVSS | max 80 mA | 48 | |
| Output current sunk by any I/O and control pin IIO | max 20 mA | 48 | |
| Output current source by any I/Os and control pin IIO | max -20 mA | 48 | |
| Injected current on NRST pin IINJ(PIN) | Limit ±4 mA | max 4 mA | 48 |
| Injected current on OSCIN pin IINJ(PIN) | Limit ±4 mA | max 4 mA | 48 |
| Injected current on any other pin IINJ(PIN) | Limit ±4 mA | max 4 mA | 48 |
| Total injected current (sum of all I/O and control pins) ΣI INJ(PIN) | Absolute sum of positive and negative injected currents; limit ±20 mA | max 20 mA | 48 |
| Storage temperature range TSTG | Absolute maximum ratings | min -65 · max 150 °C | 48 |
| Maximum junction temperature TJ | Absolute maximum ratings | max 150 °C | 48 |
| Internal CPU clock frequency fCPU | min 0 · max 16 MHz | 49 | |
| Standard operating voltage VDD | min 2.95 · max 5.5 V | 49 | |
| CEXT: capacitance of external capacitor VCAP | min 470 · max 3300 nF | 49 | |
| ESR of external capacitor VCAP | at 1 MHz | max 0.3 Ω | 49 |
| ESL of external capacitor VCAP | max 15 nH | 49 | |
| Power dissipation at TA = 85 °C for suffix 6 PD | TSSOP20 | max 238 mW | 49 |
| Ambient temperature for 6 suffix version TA | Maximum power dissipation | min -40 · max 85 °C | 49 |
| Junction temperature range for suffix 6 TJ | min -40 · max 105 °C | 49 | |
| VDD rise time rate tVDD | min 2 us/V | 50 | |
| VDD fall time rate tVDD | min 2 us/V | 50 | |
| Reset release delay tTEMP | VDD rising | max 1.7 ms | 50 |
| Power-on reset threshold VIT+ | min 2.6 · typ 2.7 · max 2.85 V | 50 | |
| Brown-out reset threshold VIT- | min 2.5 · typ 2.65 · max 2.8 V | 50 | |
| Brown-out reset hysteresis VHYS(BOR) | typ 70 mV | 50 | |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz); peripherals disabled | typ 2.3 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz); peripherals disabled | typ 2 · max 2.35 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz); peripherals disabled | typ 1.7 · max 2 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSE user ext. clock (16 MHz); peripherals disabled | typ 0.86 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz); peripherals disabled | typ 0.7 · max 0.87 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8); peripherals disabled | typ 0.46 · max 0.58 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 128 kHz; LSI RC osc. (128 kHz); peripherals disabled | typ 0.41 · max 0.55 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz); peripherals disabled | typ 4.5 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz); peripherals disabled | typ 4.3 · max 4.75 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz); peripherals disabled | typ 3.7 · max 4.5 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 2 MHz; HSI RC osc. (16 MHz/8); peripherals disabled | typ 0.84 · max 1.05 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz); peripherals disabled | typ 0.72 · max 0.9 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8); peripherals disabled | typ 0.46 · max 0.58 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 128 kHz; LSI RC osc. (128 kHz); peripherals disabled | typ 0.42 · max 0.57 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz); peripherals disabled | typ 1.8 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz); peripherals disabled | typ 2 · max 2.3 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz); peripherals disabled | typ 1.5 · max 2 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSE user ext. clock (16 MHz); peripherals disabled | typ 0.81 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8); peripherals disabled | typ 0.46 · max 0.58 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz); peripherals disabled | typ 4 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz); peripherals disabled | typ 3.9 · max 4.7 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz); peripherals disabled | typ 3.7 · max 4.5 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz); peripherals disabled | typ 0.72 · max 0.9 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8); peripherals disabled | typ 0.46 · max 0.58 mA | 52 |
| Supply current in halt mode IDD(H) | Flash in operating mode, HSI clock after wakeup; maximum at 85 °C | typ 63 · max 75 uA | 55 |
| Supply current in halt mode IDD(H) | Flash in power-down mode, HSI clock after wakeup; maximum at 85 °C | typ 6 · max 20 uA | 55 |
| Supply current in halt mode IDD(H) | Flash in operating mode, HSI clock after wakeup; maximum at 85 °C | typ 60 · max 75 uA | 55 |
| Thermal resistance junction-ambient ΘJA | TSSOP20 - 4.4 mm; JEDEC JESD51-2, 4-layer PCB, natural convection | typ 84 °C/W | 94 |
| Supply voltage VDDx - VSS | Absolute maximum ratings | min -0.3 · max 6.5 V | 47 |
| Input voltage on true open drain pins VIN | Absolute maximum ratings; minimum VSS - 0.3 V | max 6.5 V | 47 |
| Variations between different power pins |VDDx - VDD| | Absolute maximum ratings | max 50 mV | 47 |
| Variations between all the different ground pins |VSSx - VSS| | Absolute maximum ratings | max 50 mV | 47 |
| Total current into VDD power lines (source) IVDD | Absolute maximum ratings | max 100 mA | 47 |
| Total current out of VSS ground lines (sink) IVSS | Absolute maximum ratings | max 80 mA | 48 |
| Output current sunk by any I/O and control pin IIO | Absolute maximum ratings | max 20 mA | 48 |
| Output current source by any I/Os and control pin IIO | Absolute maximum ratings | max -20 mA | 48 |
| Injected current on NRST pin IINJ(PIN) | Absolute maximum ratings; ±4 mA | min -4 · max 4 mA | 48 |
| Injected current on OSCIN pin IINJ(PIN) | Absolute maximum ratings; ±4 mA | min -4 · max 4 mA | 48 |
| Injected current on any other pin IINJ(PIN) | Absolute maximum ratings; ±4 mA | min -4 · max 4 mA | 48 |
| Total injected current (sum of all I/O and control pins) ΣI INJ(PIN) | Absolute maximum ratings; ±20 mA | min -20 · max 20 mA | 48 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz); no load, peripherals disabled | typ 2.3 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz); no load, peripherals disabled | typ 2 · max 2.35 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz); no load, peripherals disabled | typ 1.7 · max 2 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSE user ext. clock (16 MHz) | typ 0.86 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz) | typ 0.7 · max 0.87 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8) | typ 0.46 · max 0.58 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 128 kHz; LSI RC osc. (128 kHz) | typ 0.41 · max 0.55 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz) | typ 4.5 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) | typ 4.3 · max 4.75 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) | typ 3.7 · max 4.5 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 2 MHz; HSI RC osc. (16 MHz/8); default clock configuration, all peripherals off | typ 0.84 · max 1.05 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz) | typ 0.72 · max 0.9 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8) | typ 0.46 · max 0.58 mA | 51 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 128 kHz; LSI RC osc. (128 kHz) | typ 0.42 · max 0.57 mA | 51 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz) | typ 1.8 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) | typ 2 · max 2.3 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) | typ 1.5 · max 2 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSE user ext. clock (16 MHz) | typ 0.81 mA | 52 |
| Supply current in run mode, code executed from RAM IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8) | typ 0.46 · max 0.58 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz) | typ 4 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) | typ 3.9 · max 4.7 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) | typ 3.7 · max 4.5 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz) | typ 0.72 · max 0.9 mA | 52 |
| Supply current in run mode, code executed from Flash IDD(RUN) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8) | typ 0.46 · max 0.58 mA | 52 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz) | typ 1.6 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) | typ 1.1 · max 1.3 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) | typ 0.89 · max 1.1 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz) | typ 0.7 · max 0.88 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8); default clock configuration, all peripherals off | typ 0.45 · max 0.57 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 128 kHz; LSI RC osc. (128 kHz) | typ 0.4 · max 0.54 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 16 MHz; HSE crystal osc. (16 MHz) | typ 1.1 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 16 MHz; HSE user ext. clock (16 MHz) | typ 1.1 · max 1.3 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 16 MHz; HSI RC osc. (16 MHz) | typ 0.89 · max 1.1 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER/128 = 125 kHz; HSI RC osc. (16 MHz) | typ 0.7 · max 0.88 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER/128 = 15.625 kHz; HSI RC osc. (16 MHz/8); default clock configuration, all peripherals off | typ 0.45 · max 0.57 mA | 53 |
| Supply current in wait mode IDD(WFI) | fCPU = fMASTER = 128 kHz; LSI RC osc. (128 kHz) | typ 0.4 · max 0.54 mA | 53 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Operating mode; HSE crystal osc. (16 MHz) | typ 1030 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Operating mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 200 · max 260 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Power-down mode; HSE crystal osc. (16 MHz) | typ 970 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Power-down mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 150 · max 200 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR Off; Flash Operating mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 66 · max 85 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR Off; Flash Power-down mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 10 · max 20 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Operating mode; HSE crystal osc. (16 MHz) | typ 550 uA | 54 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Operating mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 200 · max 260 uA | 55 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Power-down mode; HSE crystal osc. (16 MHz) | typ 970 uA | 55 |
| Supply current in active halt mode IDD(AH) | MVR On; Flash Power-down mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 150 · max 200 uA | 55 |
| Supply current in active halt mode IDD(AH) | MVR Off; Flash Operating mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 66 · max 80 uA | 55 |
| Supply current in active halt mode IDD(AH) | MVR Off; Flash Power-down mode; LSI RC osc. (128 kHz); maximum at 85 °C | typ 10 · max 18 uA | 55 |
| Supply current in reset state IDD(R) | VDD = 5 V; all I/Os tied to VSS | typ 400 uA | 57 |
| Supply current in reset state IDD(R) | VDD = 3.3 V; all I/Os tied to VSS | typ 300 uA | 57 |
| Reset pin release to vector fetch tRESETBL | max 150 us | 57 | |
| TIM1 supply current IDD(TIM1) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, counter running, no IC/OC programmed | typ 210 uA | 57 |
| TIM2 supply current IDD(TIM2) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, counter running, no IC/OC programmed | typ 130 uA | 57 |
| TIM4 timer supply current IDD(TIM4) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, counter running, no IC/OC programmed | typ 50 uA | 57 |
| UART1 supply current IDD(UART1) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, peripheral clocked and released from reset, no I/O pads toggling | typ 120 uA | 57 |
| SPI supply current IDD(SPI) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, peripheral clocked and released from reset, no I/O pads toggling | typ 45 uA | 57 |
| I C supply current IDD(I2C) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, peripheral clocked and released from reset, no I/O pads toggling | typ 65 uA | 57 |
| ADC1 supply current when converting IDD(ADC1) | HSI internal RC; fCPU = fMASTER = 16 MHz; VDD = 5 V; differential current, continuous A/D conversions | typ 1000 uA | 57 |
| User external clock source frequency fHSE_ext | General operating conditions for VDD and TA | min 0 · max 16 MHz | 60 |
| OSCIN input leakage current ILEAK_HSE | VSS < VIN < VDD | min -1 · max 1 uA | 60 |
| External high speed oscillator frequency fHSE | min 1 · max 16 MHz | 61 | |
| Feedback resistor RF | typ 220 kΩ | 61 | |
| Recommended load capacitance C | C is approximately equivalent to 2 x crystal Cload | max 20 pF | 61 |
| HSE oscillator power consumption IDD(HSE) | C = 20 pF, fOSC = 16 MHz, startup | max 6 mA | 61 |
| HSE oscillator power consumption IDD(HSE) | C = 20 pF, fOSC = 16 MHz, stabilized | max 1.6 mA | 61 |
| HSE oscillator power consumption IDD(HSE) | C = 10 pF, fOSC = 16 MHz, startup | max 6 mA | 61 |
| HSE oscillator power consumption IDD(HSE) | C = 10 pF, fOSC = 16 MHz, stabilized | max 1.2 mA | 61 |
| Oscillator transconductance gm | min 5 mA/V | 61 | |
| Startup time tSU(HSE) | VDD is stabilized | typ 1 ms | 61 |
| Frequency fHSI | typ 16 MHz | 62 | |
| Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/64 bytes) tprog | typ 6 · max 6.6 ms | 65 | |
| Fast programming time for 1 block (64 bytes) tprog | typ 3 · max 3.33 ms | 65 | |
| Erase time for 1 block (64 bytes) terase | typ 3 · max 3.33 ms | 65 | |
| Erase/write cycles (program memory) NRW | TA = 85 °C | min 100 cycles | 65 |
| Erase/write cycles (data memory) NRW | TA = 85 °C | min 100 k cycles | 65 |
| Data retention (program memory) after 100 erase/write cycles at TA = 85 °C tRET | TRET = 55°C | min 20 years | 65 |
| Data retention (data memory) after 10 k erase/write cycles at TA = 85 °C tRET | TRET = 55°C | min 20 years | 65 |
| Data retention (data memory) after 100 k erase/write cycles at TA = 85 °C tRET | TRET = 85°C | min 1 years | 65 |
| Supply current (Flash programming or erasing for 1 to 128 bytes) IDD | typ 2 mA | 65 | |
| Output low level with 8 pins sunk VOL | IIO = 10 mA, VDD = 5 V | max 2 V | 68 |
| Output low level with 4 pins sunk VOL | IIO = 4 mA, VDD = 3.3 V | max 1 V | 68 |
| Output high level with 8 pins sourced VOH | IIO = 10 mA, VDD = 5 V | min 2.8 V | 68 |
| Output high level with 4 pins sourced VOH | IIO = 4 mA, VDD = 3.3 V | min 2.1 V | 68 |
| Output low level with 2 pins sunk VOL | IIO = 10 mA, VDD = 5 V | max 1 V | 68 |
| Output low level with 2 pins sunk VOL | IIO = 10 mA, VDD = 3.3 V | max 1.5 V | 68 |
| Output low level with 2 pins sunk VOL | IIO = 20 mA, VDD = 5 V | max 2 V | 69 |
| Output low level with 8 pins sunk VOL | IIO = 10 mA, VDD = 5 V | max 0.8 V | 69 |
| Output low level with 4 pins sunk VOL | IIO = 10 mA, VDD = 3.3 V | max 1 V | 69 |
| Output low level with 4 pins sunk VOL | IIO = 20 mA, VDD = 5 V | max 1.5 V | 69 |
| Output high level with 8 pins sourced VOH | IIO = 10 mA, VDD = 5 V | min 4 V | 69 |
| Output high level with 4 pins sourced VOH | IIO = 10 mA, VDD = 3.3 V | min 2.1 V | 69 |
| Output high level with 4 pins sourced VOH | IIO = 20 mA, VDD = 5 V | min 3.3 V | 69 |
| STOP condition setup time tsu(STO) | Standard mode I²C | min 4 us | 81 |
| STOP condition setup time tsu(STO) | Fast mode I²C | min 0.6 us | 81 |
| STOP to START condition time (bus free) tw(STO:STA) | Standard mode I²C | min 4.7 us | 81 |
| STOP to START condition time (bus free) tw(STO:STA) | Fast mode I²C | min 1.3 us | 81 |
| Capacitive load for each bus line Cb | Standard mode I²C | max 400 pF | 81 |
| Capacitive load for each bus line Cb | Fast mode I²C | max 400 pF | 81 |
| ADC clock frequency fADC | VDD =2.95 to 5.5 V | min 1 · max 4 MHz | 82 |
| ADC clock frequency fADC | VDD =4.5 to 5.5 V | min 1 · max 6 MHz | 82 |
| Internal sample and hold capacitor CADC | typ 3 pF | 82 | |
| Minimum sampling time tS | fADC = 4 MHz | typ 0.75 us | 82 |
| Minimum sampling time tS | fADC = 6 MHz | typ 0.5 us | 82 |
| Wake-up time from standby tSTAB | typ 7 us | 82 | |
| Minimum total conversion time (including sampling time, 10-bit resolution) tCONV | fADC = 4 MHz | min 3.5 us | 82 |
| Minimum total conversion time (including sampling time, 10-bit resolution) tCONV | fADC = 6 MHz | min 2.33 us | 82 |
| Minimum total conversion time (including sampling time, 10-bit resolution) tCONV | min 14 1/fADC | 82 | |
| Total unadjusted error |ET| | fADC = 2 MHz | typ 1.6 · max 3.5 LSB | 82 |
| Total unadjusted error |ET| | fADC = 4 MHz | typ 2.2 · max 4 LSB | 82 |
| Total unadjusted error |ET| | fADC = 6 MHz | typ 2.4 · max 4.5 LSB | 82 |
| Offset error |EO| | fADC = 2 MHz | typ 1.1 · max 2.5 LSB | 82 |
| Electrostatic discharge voltage (Human body model) VESD(HBM) | TA = 25°C, conforming to JESD22-A114; Class A | max 4000 V | 87 |
Pins, by the datasheet
15- 2 UART1_TX/AIN5/(HS) PD5
- Port D5; UART1 transmit or analog input 5; high sink capability. · p. 21
- 3 UART1_RX/AIN6/(HS) PD6
- Port D6; UART1 receive or analog input 6; high sink capability. · p. 21
- 4 NRST
- Reset. · p. 21
- 5 OSCIN/PA1
- Port A1 or oscillator input; automatically input weak pull-up in halt/active-halt and unavailable for wakeup. · p. 21
- 6 OSCOUT/PA2
- Port A2 or oscillator output. · p. 21
- 7 VSS
- Ground; connect to the external power supply ground. · p. 21
- 8 VCAP
- External capacitor connection. · p. 21
- 9 VDD
- Supply voltage; connect to the external power supply. · p. 21
- 10 [SPI_NSS] TIM2_CH3/(HS) PA3
- Port A3; Timer 2 channel 3 or remapped SPI NSS; high sink capability. · p. 21
- 11 PB5
- True open-drain Port B5; I²C SDA or remapped TIM1 break input. · p. 21
- 12 PB4
- True open-drain Port B4; I²C SCL or remapped ADC external trigger. · p. 21
- 13 PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
- Port C3; TIM1 channel 3, remapped top level interrupt or TIM1 complementary channel 1; high sink capability. · p. 21
- 14 PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
- Port C4; TIM1 channel 4, clock output, analog input 2 or remapped TIM1 complementary channel 2; high sink capability. · p. 21
- 15 PC5 (HS)/SPI_SCK [TIM2_CH1]
- Port C5; SPI clock or remapped TIM2 channel 1; high sink capability. · p. 21
- 18 PD1/ SWIM
- Port D1 or SWIM data interface; input pull-up during reset and after internal reset release. · p. 20
- 2 layers87 × 71 mm

- 2 layers32.1 × 41.2 mm

Ir signalgen lite
dilshan/ir-clone
Open-source infrared remote control signal analysis and generating tool
40 parts58MIT - 4 layers26.4 × 56 mm

RPI5-SDexpress Hat
will127534/RPI5-SDexpress-Hat
ctrl-c "RPI5-CFE-Hat" ctrl-v "RPI5-SDexpress-Hat"
51 parts37MIT - 4 layers65 × 56 mm

- 4 layers

Kvm base
thatoddmailbox/kvm-base
The main board for the open-source HDMI KVM switch I built.
70 parts19 - 2 layers

Ctrl brd reduced
alsav/stm8-soldering-station-controller
Tomizawa FZ-880B soldering station controller open-source firmware
14 parts12 - 2 layers72.8 × 32 mm

- 2 layers65 × 56 mm

Ras pi supercap ups
akuker/SuperUPS
This is a fork of the original Supercapacitor UPS board for a Raspberry Pi by Scott Baker, http://www.smbaker.com/
88 parts7
Parts like it
8STC8H1K08-36I-TSSOP20
TSSOP-201.9V~5.5V 10bit 17 51 Family 8KB FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSSTC MicroMicrocontrollers (MCU/MPU/SOC)STM32F030F4P6
TSSOP-20-40℃~+85℃ 12bit 15 16KB 2.4V~3.6V 32 Bit 48MHz 4KB ARM Cortex-M0 Built-in FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSSTMicroelectronicsMicrocontrollers (MCU/MPU/SOC)PY32F002AF15P6TR
TSSOP-20TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSPUYAMicrocontrollers (MCU/MPU/SOC)PY32F002AF15P6TU
TSSOP-201.7V~5.5V 12bit 20KB 24MHz ARM Cortex-M0 FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSPUYAMicrocontrollers (MCU/MPU/SOC)PY32F003F18P6TR
TSSOP-20TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSPUYAMicrocontrollers (MCU/MPU/SOC)N76E003AT20-T
TSSOP-2012bit 17 18KB 2.4V~5.5V 51 Family FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSNUVOTONMicrocontrollers (MCU/MPU/SOC)CH32V003F4P6
TSSOP-20-175milTSSOP-20-175mil Microcontrollers (MCU/MPU/SOC) ROHSWCH (Nanjing Qinheng Microelectronics)Microcontrollers (MCU/MPU/SOC)STM32G030F6P6
TSSOP-20-40℃~+85℃ 12bit 17 2V~3.6V 32 Bit 32KB 64MHz 8KB ARM Cortex-M0+ Built-in+External FLASH TSSOP-20 Microcontrollers (MCU/MPU/SOC) ROHSSTMicroelectronicsMicrocontrollers (MCU/MPU/SOC)
Questions
Is there a KiCad symbol and footprint for the STM8S003F3P6?
Yes. The symbol is EasyEDA_Pro:STM8S003F3P6 and the footprint Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm, both drawn on this page. PCBKit places them on a board for you when you design with it.
What package is the STM8S003F3P6?
TSSOP-20, with 20 pins. Its footprint is drawn on this page.
Where is the STM8S003F3P6 datasheet?
STMicroelectronics publishes it: the Datasheet link on this page opens it.
Where can I order the STM8S003F3P6?
JLCPCB lists it as part C52717, with 154,831 in stock; the sellers' links on this page open their listings.
What can replace the STM8S003F3P6?
Parts like it in the library: the STC8H1K08-36I-TSSOP20 by STC Micro, the STM32F030F4P6 by STMicroelectronics, the PY32F002AF15P6TR by PUYA and the PY32F002AF15P6TU by PUYA. Check their datasheets: a part that fits the footprint may still differ in its ratings.
Which open-source boards use the STM8S003F3P6?
43 boards in 39 repositories on GitHub; the most starred are listed on this page, with their KiCad files.