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PCAL6416AHF, in 3D

PCAL6416AHF

NXP Semiconductors

-40℃~+85℃ 1.65V~5.5V 16 1uA 2 25mA 400kHz I2C、SMBus Interrupt Output Push-Pull、Open-drain Reset function、Cascading and address extension、Built-in LED driver、IO level configurable HWQFN-24 I/O Expanders ROHS

Extended
DatasheetJLCPCBLCSCnxp/PCAL6416AHF
Category
I, O Expanders
Package
HWQFN-24
Pins
25

Overview

The PCAL6416AHF is an i, O Expander made by NXP Semiconductors in a HWQFN-24 package with 25 pins. -40℃~+85℃ 1.65V~5.5V 16 1uA 2 25mA 400kHz I2C、SMBus Interrupt Output Push-Pull、Open-drain Reset function、Cascading and address extension、Built-in LED driver、IO level configurable HWQFN-24 I/O Expanders ROHS.

PCBKit's library has its KiCad symbol (Interface_Expansion:PCAL6416AHF, from KiCad's library) and its footprint (Package_DFN_QFN:HVQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm, from KiCad's library), ready for a KiCad board. 9,748 are in stock at JLCPCB (part C2652287). 8 open-source boards in 8 repositories on GitHub use it.

Symbol

P0_01P0_12P0_23P0_34P0_45P0_56P0_67P0_78V_{SS}9P1_010P1_111P1_212P1_313P1_414P1_515P1_616P1_717ADDR18SCL19SDA20V_{DD(P)}21INT22V_{DD(I2C-bus)}23RESET24EP25
Interface_Expansion:PCAL6416AHFFrom KiCad's library

Footprint

25
Package_DFN_QFN:HVQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mmFrom KiCad's library

From the datasheet

16
Supply, least
1.65 V · VDD(I2C-bus), recommended operating min · p. 27
Supply, most
5.5 V · VDD(I2C-bus), recommended operating max · p. 27
Supply, absolute maximum
6.5 V · VDD(I2C-bus), absolute max · p. 26
Works from
-40 °C · ambient, operating in free air min · p. 27
Works up to
85 °C · ambient, operating in free air max · p. 27
Junction, hottest
125 °C · junction temperature max · p. 27
A pin gives at most
50 mA · P port continuous LOW-level output current absolute max · p. 27
A pin gives at most
25 mA · P port continuous HIGH-level output current absolute max · p. 27
Takes working
60 µA · sum of IDD(I2C-bus) and IDD(P), active continuous register read at 400 kHz, VDD(P) = 3.6–5.5 V, typical · p. 29
Takes working
40 µA · sum of IDD(I2C-bus) and IDD(P), active continuous register read at 400 kHz, VDD(P) = 2.3–3.6 V, typical · p. 29
Takes working
20 µA · sum of IDD(I2C-bus) and IDD(P), active continuous register read at 400 kHz, VDD(P) = 1.65–2.3 V, typical · p. 29
Takes at most
125 µA · sum of IDD(I2C-bus) and IDD(P), active continuous register read at 400 kHz, VDD(P) = 3.6–5.5 V, max · p. 29
Takes asleep
1.5 µA · sum of IDD(I2C-bus) and IDD(P), fSCL = 0 kHz, VDD(P) = 3.6–5.5 V, typical · p. 29
Takes asleep
1 µA · sum of IDD(I2C-bus) and IDD(P), fSCL = 0 kHz, VDD(P) = 2.3–3.6 V, typical · p. 29
Takes asleep
500 nA · sum of IDD(I2C-bus) and IDD(P), fSCL = 0 kHz, VDD(P) = 1.65–2.3 V, typical · p. 29
Data rate, most
400 kbit/s · Fast-mode I2C SCL clock frequency max · p. 34

What it is and has

16
GPIO
16-bit general-purpose I/O expander · p. 1
Voltage translation
Bidirectional voltage-level translation and GPIO expansion · p. 2
I/O tolerance
5 V tolerant I/O ports · p. 2
Reset
Active LOW reset input · p. 2
Interrupt
Open-drain active LOW interrupt output · p. 2
Power-on reset
Internal · p. 2
Power-up configuration
All channels configured as inputs · p. 2
Input filtering
Noise filter on SCL/SDA inputs · p. 2
Output configuration
Bank selectable push-pull or open-drain output stages · p. 3
Output drive strength
Four programmable drive strengths · p. 3
Internal pull resistors
100 kΩ selectable pull-up/pull-down · p. 3
Interrupt status
Read-only register identifies interrupt source · p. 3
ESD protection
2000 V Human-Body Model (A114-A) · p. 2
ESD protection
1000 V Charged-Device Model (C101) · p. 2
Level shifting
Built-in level shifting · p. 1
Input resistors
Programmable pull-up and pull-down resistors · p. 25

Around it

4
res not specified
between INT and VDD(I2C-bus) or VDD(P); Interrupt output pull-up resistor. · p. 5
res not specified
between RESET and VDD(I2C-bus); Pull-up required if no active connection is used. · p. 15
res not specified
between SCL and VDD(I2C-bus); Serial clock bus pull-up resistor. · p. 6
res not specified
between SDA and VDD(I2C-bus); Serial data bus pull-up resistor. · p. 6

Specifications

145
ParameterConditionsAs printedPage
I C-bus supply voltage VDD(I2C-bus)min -0.5 · max 6.5 V26
supply voltage port P VDD(P)min -0.5 · max 6.5 V26
input voltage VINegative-voltage rating may be exceeded if current ratings are observed.min -0.5 · max 6.5 V27
output voltage VOVoltage rating may be exceeded if current ratings are observed.min -0.5 · max 6.5 V27
input clamping current IIKADDR, RESET, SCL; VI < 0 Vmax 20 mA27
output clamping current IOKINT; VO < 0 Vmax 20 mA27
input/output clamping current IIOKP port; VO < 0 V or VO > VDD(P)max 20 mA27
input/output clamping current IIOKSDA; VO < 0 V or VO > VDD(I2C-bus)max 20 mA27
LOW-level output current IOLcontinuous; P port; VO = 0 V to VDD(P)max 50 mA27
LOW-level output current IOLcontinuous; SDA, INT; VO = 0 V to VDD(I2C-bus)max 25 mA27
HIGH-level output current IOHcontinuous; P port; VO = 0 V to VDD(P)max 25 mA27
supply current IDDcontinuous through VSSmax 200 mA27
supply current port P IDD(P)continuous through VDD(P)max 160 mA27
I C-bus supply current IDD(I2C-bus)continuous through VDD(I2C-bus)max 10 mA27
storage temperature Tstgmin -65 · max 150 °C27
maximum junction temperature Tj(max)max 125 °C27
I C-bus supply voltage VDD(I2C-bus)min 1.65 · max 5.5 V27
supply voltage port P VDD(P)min 1.65 · max 5.5 V27
HIGH-level input voltage VIHSCL, SDA, RESET; minimum = 0.7 × VDD(I2C-bus)max 5.5 V27
HIGH-level input voltage VIHADDR, P1_7 to P0_0; minimum = 0.7 × VDD(P)max 5.5 V27
LOW-level input voltage VILSCL, SDA, RESET; maximum = 0.3 × VDD(I2C-bus)min -0.5 V27
LOW-level input voltage VILADDR, P1_7 to P0_0; maximum = 0.3 × VDD(P)min -0.5 V27
HIGH-level output current IOHP1_7 to P0_0max 10 mA27
LOW-level output current IOLP1_7 to P0_0max 25 mA27
ambient temperature Tamboperating in free airmin -40 · max 85 °C27
transient thermal impedance from junction to ambient Zth(j-a)HWQFN24 package; calculated in accordance with JESD 51-7max 66 K/W27
input clamping voltage VIKII = -18 mAmin -1.2 V28
power-on reset voltage VPORVI = VDD(P) or VSS; IO = 0 mAtyp 1.1 · max 1.4 V28
HIGH-level output voltage VOHP port; IOH = -8 mA; CCX.X = 11b; VDD(P) = 1.65 Vmin 1.2 V28
HIGH-level output voltage VOHP port; IOH = -8 mA; CCX.X = 11b; VDD(P) = 2.3 Vmin 1.8 V28
HIGH-level output voltage VOHP port; IOH = -8 mA; CCX.X = 11b; VDD(P) = 3 Vmin 2.6 V28
HIGH-level output voltage VOHP port; IOH = -8 mA; CCX.X = 11b; VDD(P) = 4.5 Vmin 4.1 V28
HIGH-level output voltage VOHP port; IOH = -2.5 mA and CCX.X = 00b; IOH = -5 mA and CCX.X = 01b; IOH = -7.5 mA and CCX.X = 10b; IOH = -10 mA and CCX.X = 11b; VDD(P) = 1.65 Vmin 1.1 V28
HIGH-level output voltage VOHP port; IOH = -2.5 mA and CCX.X = 00b; IOH = -5 mA and CCX.X = 01b; IOH = -7.5 mA and CCX.X = 10b; IOH = -10 mA and CCX.X = 11b; VDD(P) = 2.3 Vmin 1.7 V28
HIGH-level output voltage VOHP port; IOH = -2.5 mA and CCX.X = 00b; IOH = -5 mA and CCX.X = 01b; IOH = -7.5 mA and CCX.X = 10b; IOH = -10 mA and CCX.X = 11b; VDD(P) = 3 Vmin 2.5 V28
HIGH-level output voltage VOHP port; IOH = -2.5 mA and CCX.X = 00b; IOH = -5 mA and CCX.X = 01b; IOH = -7.5 mA and CCX.X = 10b; IOH = -10 mA and CCX.X = 11b; VDD(P) = 4.5 Vmin 4 V28
LOW-level output voltage VOLP port; IOL = 8 mA; CCX.X = 11b; VDD(P) = 1.65 Vmax 0.45 V28
LOW-level output voltage VOLP port; IOL = 8 mA; CCX.X = 11b; VDD(P) = 2.3 Vmax 0.25 V28
LOW-level output voltage VOLP port; IOL = 8 mA; CCX.X = 11b; VDD(P) = 3 Vmax 0.25 V28
LOW-level output voltage VOLP port; IOL = 8 mA; CCX.X = 11b; VDD(P) = 4.5 Vmax 0.2 V28
LOW-level output voltage VOLP port; IOL = 2.5 mA and CCX.X = 00b; IOL = 5 mA and CCX.X = 01b; IOL = 7.5 mA and CCX.X = 10b; IOL = 10 mA and CCX.X = 11b; VDD(P) = 1.65 Vmax 0.5 V28
LOW-level output voltage VOLP port; IOL = 2.5 mA and CCX.X = 00b; IOL = 5 mA and CCX.X = 01b; IOL = 7.5 mA and CCX.X = 10b; IOL = 10 mA and CCX.X = 11b; VDD(P) = 2.3 Vmax 0.3 V28
LOW-level output voltage VOLP port; IOL = 2.5 mA and CCX.X = 00b; IOL = 5 mA and CCX.X = 01b; IOL = 7.5 mA and CCX.X = 10b; IOL = 10 mA and CCX.X = 11b; VDD(P) = 3 Vmax 0.25 V28
LOW-level output voltage VOLP port; IOL = 2.5 mA and CCX.X = 00b; IOL = 5 mA and CCX.X = 01b; IOL = 7.5 mA and CCX.X = 10b; IOL = 10 mA and CCX.X = 11b; VDD(P) = 4.5 Vmax 0.2 V28
LOW-level output current IOLVOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V; SDAmin 3 mA28
LOW-level output current IOLVOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V; INTmin 3 · typ 15 mA29
input current IIVDD(P) = 1.65 V to 5.5 V; SCL, SDA, RESET; VI = VDD(I2C-bus) or VSSmax 1 uA29
input current IIVDD(P) = 1.65 V to 5.5 V; ADDR; VI = VDD(P) or VSSmax 1 uA29
HIGH-level input current IIHP port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 Vmax 1 uA29
LOW-level input current IILP port; VI = VSS; VDD(P) = 1.65 V to 5.5 Vmax 1 uA29
supply current IDDIDD(I2C-bus) + IDD(P); SDA, P port, ADDR, RESET; VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD(P) = 3.6 V to 5.5 Vtyp 10 · max 25 uA29
supply current IDDIDD(I2C-bus) + IDD(P); SDA, P port, ADDR, RESET; VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD(P) = 2.3 V to 3.6 Vtyp 6.5 · max 15 uA29
supply current IDDIDD(I2C-bus) + IDD(P); SDA, P port, ADDR, RESET; VI on SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz; VDD(P) = 1.65 V to 2.3 Vtyp 4 · max 9 uA29
supply current IDDIDD(I2C-bus) + IDD(P); SCL, SDA, P port, ADDR, RESET; VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD(P) = 3.6 V to 5.5 Vtyp 1.5 · max 7 uA29
supply current IDDIDD(I2C-bus) + IDD(P); SCL, SDA, P port, ADDR, RESET; VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD(P) = 2.3 V to 3.6 Vtyp 1 · max 3.2 uA29
supply current IDDIDD(I2C-bus) + IDD(P); SCL, SDA, P port, ADDR, RESET; VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS; VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 0 kHz; VDD(P) = 1.65 V to 2.3 Vtyp 0.5 · max 1.7 uA29
supply current IDDActive mode; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on RESET = VDD(I2C-bus); VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz, continuous register read; VDD(P) = 3.6 V to 5.5 Vtyp 60 · max 125 uA29
supply current IDDActive mode; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on RESET = VDD(I2C-bus); VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz, continuous register read; VDD(P) = 2.3 V to 3.6 Vtyp 40 · max 75 uA29
supply current IDDActive mode; IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on RESET = VDD(I2C-bus); VI on P port and ADDR = VDD(P); IO = 0 mA; I/O = inputs; fSCL = 400 kHz, continuous register read; VDD(P) = 1.65 V to 2.3 Vtyp 20 · max 45 uA29
supply current IDDwith pull-ups enabled (PCAL6416A only); IDD(I2C-bus) + IDD(P); P port, ADDR, RESET; VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS; VI on P port = VSS; VI on ADDR = VDD(I2C-bus) or VSS; IO = 0 mA; I/O = inputs with pull-up enabled; fSCL = 0 kHz; VDD(P) = 1.65 V to 5.5 Vtyp 1.1 · max 1.5 mA29
SCL clock frequency fSCLStandard-mode I C-busmin 0 · max 100 kHz34
SCL clock frequency fSCLFast-mode I C-busmin 0 · max 400 kHz34
HIGH period of the SCL clock tHIGHStandard-mode I C-busmin 4 us34
HIGH period of the SCL clock tHIGHFast-mode I C-busmin 0.6 us34
LOW period of the SCL clock tLOWStandard-mode I C-busmin 4.7 us34
LOW period of the SCL clock tLOWFast-mode I C-busmin 1.3 us34
pulse width of spikes that must be suppressed by the input filter tSPStandard-mode I C-busmin 0 · max 50 ns34
pulse width of spikes that must be suppressed by the input filter tSPFast-mode I C-busmin 0 · max 50 ns34
data set-up time tSU;DATStandard-mode I C-busmin 250 ns34
data set-up time tSU;DATFast-mode I C-busmin 100 ns34
data hold time tHD;DATStandard-mode I C-busmin 0 ns34
data hold time tHD;DATFast-mode I C-busmin 0 ns34
rise time of both SDA and SCL signals trStandard-mode I C-busmax 1000 ns34
rise time of both SDA and SCL signals trFast-mode I C-busmin 20 · max 300 ns34
fall time of both SDA and SCL signals tfStandard-mode I C-busmax 300 ns34
fall time of both SDA and SCL signals tfFast-mode I C-bus; minimum = 20 × (VDD / 5.5 V) nsmax 300 ns34
bus free time between a STOP and START condition tBUFStandard-mode I C-busmin 4.7 us34
bus free time between a STOP and START condition tBUFFast-mode I C-busmin 1.3 us34
set-up time for a repeated START condition tSU;STAStandard-mode I C-busmin 4.7 us34
set-up time for a repeated START condition tSU;STAFast-mode I C-busmin 0.6 us34
hold time (repeated) START condition tHD;STAStandard-mode I C-busmin 4 us34
hold time (repeated) START condition tHD;STAFast-mode I C-busmin 0.6 us34
set-up time for STOP condition tSU;STOStandard-mode I C-busmin 4 us34
set-up time for STOP condition tSU;STOFast-mode I C-busmin 0.6 us34
data valid time tVD;DATStandard-mode I C-bus; SCL LOW to SDA output validmax 3.45 us34
data valid time tVD;DATFast-mode I C-bus; SCL LOW to SDA output validmax 0.9 us34
data valid acknowledge time tVD;ACKStandard-mode I C-bus; ACK signal from SCL LOW to SDA (out) LOWmax 3.45 us35
data valid acknowledge time tVD;ACKFast-mode I C-bus; ACK signal from SCL LOW to SDA (out) LOWmax 0.9 us35
reset pulse width tw(rst)Standard-mode I C-busmin 30 ns35
reset pulse width tw(rst)Fast-mode I C-busmin 30 ns35
reset recovery time trec(rst)Standard-mode I C-busmin 200 ns35
reset recovery time trec(rst)Fast-mode I C-busmin 200 ns35
reset time trstStandard-mode I C-bus; minimum time for SDA to become HIGH or minimum time to wait before doing a STARTmin 600 ns35
reset time trstFast-mode I C-bus; minimum time for SDA to become HIGH or minimum time to wait before doing a STARTmin 600 ns35
valid time on pin INT tv(INT)Standard-mode I C-bus; from P port to INT; CL ≤ 100 pFmax 1 us35
valid time on pin INT tv(INT)Fast-mode I C-bus; from P port to INT; CL ≤ 100 pFmax 1 us35
reset time on pin INT trst(INT)Standard-mode I C-bus; from SCL to INT; CL ≤ 100 pFmax 1 us35
reset time on pin INT trst(INT)Fast-mode I C-bus; from SCL to INT; CL ≤ 100 pFmax 1 us35
data output valid time tv(Q)Standard-mode I C-bus; from SCL to P port; CL ≤ 100 pFmax 400 ns35
data output valid time tv(Q)Fast-mode I C-bus; from SCL to P port; CL ≤ 100 pFmax 400 ns35
data input set-up time tsu(D)Standard-mode I C-bus; from P port to SCL; CL ≤ 100 pFmin 0 ns35
data input set-up time tsu(D)Fast-mode I C-bus; from P port to SCL; CL ≤ 100 pFmin 0 ns35
data input hold time th(D)Standard-mode I C-bus; from P port to SCL; CL ≤ 100 pFmin 300 ns35
data input hold time th(D)Fast-mode I C-bus; from P port to SCL; CL ≤ 100 pFmin 300 ns35
input voltage VIRatings may be exceeded if input and output current ratings are observed.min -0.5 · max 6.5 V27
output voltage VORatings may be exceeded if input and output current ratings are observed.min -0.5 · max 6.5 V27
HIGH-level input voltage VIHSCL, SDA, RESETmax 5.5 V27
HIGH-level input voltage VIHADDR, P1_7 to P0_0max 5.5 V27
LOW-level input voltage VILSCL, SDA, RESETmin -0.5 V27
LOW-level input voltage VILADDR, P1_7 to P0_0min -0.5 V27
LOW-level output current IOLSDA; VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 Vmin 3 mA28
LOW-level output current IOLINT; VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V; typical at Tamb = 25 °C, VDD(I2C-bus) = VDD(P) = 3.3 V; for supplies < 2.5 V, typical at VOL = 0.6 Vmin 3 · typ 15 mA29
additional quiescent supply current ΔIDDSCL, SDA, RESET; one input at VDD(I2C-bus) - 0.6 V, other inputs at VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V; internal pull-up/pull-down resistors disabledmax 25 uA30
additional quiescent supply current ΔIDDP port, ADDR; one input at VDD(P) - 0.6 V, other inputs at VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V; internal pull-up/pull-down resistors disabledmax 80 uA30
input capacitance CiVI = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 Vtyp 6 · max 7 pF30
input/output capacitance CioVI/O = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 Vtyp 7 · max 8 pF30
input/output capacitance CioVI/O = VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 Vtyp 7.5 · max 8.5 pF30
internal pull-up resistance Rpu(int)input/outputmin 50 · typ 100 · max 150 kΩ30
internal pull-down resistance Rpd(int)input/outputmin 50 · typ 100 · max 150 kΩ30
SCL clock frequency fSCLStandard-mode I2C-busmin 0 · max 100 kHz34
SCL clock frequency fSCLFast-mode I2C-busmin 0 · max 400 kHz34
HIGH period of the SCL clock tHIGHStandard-mode I2C-busmin 4 us34
HIGH period of the SCL clock tHIGHFast-mode I2C-busmin 0.6 us34
LOW period of the SCL clock tLOWStandard-mode I2C-busmin 4.7 us34
LOW period of the SCL clock tLOWFast-mode I2C-busmin 1.3 us34
pulse width of spikes that must be suppressed by the input filter tSPStandard-mode I2C-busmin 0 · max 50 ns34
pulse width of spikes that must be suppressed by the input filter tSPFast-mode I2C-busmin 0 · max 50 ns34
data set-up time tSU;DATStandard-mode I2C-busmin 250 ns34
data set-up time tSU;DATFast-mode I2C-busmin 100 ns34
data hold time tHD;DATStandard-mode I2C-busmin 0 ns34
data hold time tHD;DATFast-mode I2C-busmin 0 ns34
rise time of both SDA and SCL signals trStandard-mode I2C-busmax 1000 ns34
rise time of both SDA and SCL signals trFast-mode I2C-busmin 20 · max 300 ns34
fall time of both SDA and SCL signals tfStandard-mode I2C-busmax 300 ns34
fall time of both SDA and SCL signals tfFast-mode I2C-bus; minimum = 20 × (VDD / 5.5 V) nsmax 300 ns34
bus free time between a STOP and START condition tBUFStandard-mode I2C-busmin 4.7 us34
bus free time between a STOP and START condition tBUFFast-mode I2C-busmin 1.3 us34
set-up time for a repeated START condition tSU;STAStandard-mode I2C-busmin 4.7 us34
set-up time for a repeated START condition tSU;STAFast-mode I2C-busmin 0.6 us34
hold time (repeated) START condition tHD;STAStandard-mode I2C-busmin 4 us34
hold time (repeated) START condition tHD;STAFast-mode I2C-busmin 0.6 us34
set-up time for STOP condition tSU;STOStandard-mode I2C-busmin 4 us34
set-up time for STOP condition tSU;STOFast-mode I2C-busmin 0.6 us34
data valid time tVD;DATStandard-mode I2C-bus; SCL LOW to SDA output validmax 3.45 us34
data valid time tVD;DATFast-mode I2C-bus; SCL LOW to SDA output validmax 0.9 us34

Pins, by the datasheet

24
1 P0_0
Port 0 input/output 0; configured as input at power-on. · p. 6
2 P0_1
Port 0 input/output 1; configured as input at power-on. · p. 6
3 P0_2
Port 0 input/output 2; configured as input at power-on. · p. 6
4 P0_3
Port 0 input/output 3; configured as input at power-on. · p. 6
5 P0_4
Port 0 input/output 4; configured as input at power-on. · p. 6
6 P0_5
Port 0 input/output 5; configured as input at power-on. · p. 6
7 P0_6
Port 0 input/output 6; configured as input at power-on. · p. 6
8 P0_7
Port 0 input/output 7; configured as input at power-on. · p. 6
9 VSS
Ground. · p. 6
10 P1_0
Port 1 input/output 0; configured as input at power-on. · p. 6
11 P1_1
Port 1 input/output 1; configured as input at power-on. · p. 6
12 P1_2
Port 1 input/output 2; configured as input at power-on. · p. 6
13 P1_3
Port 1 input/output 3; configured as input at power-on. · p. 6
14 P1_4
Port 1 input/output 4; configured as input at power-on. · p. 6
15 P1_5
Port 1 input/output 5; configured as input at power-on. · p. 6
16 P1_6
Port 1 input/output 6; configured as input at power-on. · p. 6
17 P1_7
Port 1 input/output 7; configured as input at power-on. · p. 6
18 ADDR
Address input; connect directly to VDD(P) or ground. · p. 6
19 SCL
Serial clock bus; connect to VDD(I2C-bus) through a pull-up resistor. · p. 6
20 SDA
Serial data bus; connect to VDD(I2C-bus) through a pull-up resistor. · p. 6
21 VDD(P)
Supply voltage of PCAL6416A for Port P. · p. 6
22 INT
Active LOW interrupt output; connect to VDD(I2C-bus) or VDD(P) through a pull-up resistor. · p. 5
23 VDD(I2C-bus)
I2C-bus supply; connect directly to the external I2C master's VDD; provides voltage-level translation. · p. 5
24 RESET
Active LOW reset input; connect to VDD(I2C-bus) through a pull-up resistor if no active connection is used. · p. 6

Ordering codes, by the datasheet

1
PCAL6416AHF,128
HWQFN24 · Reel 13" Q2/T3; minimum order quantity 6000; Tamb = -40 °C to +85 °C. · p. 3

Parameters

18
Clock Frequency
400kHz
Current - Output Low(IOL)
25mA
Current - Supply
60uA
Current - Supply(Max)
125uA
Data Rate
400kbps
Features
IO level configurable
Interface
SMBus
Interrupt Output
Interrupt Output
Junction Temperature(Max)
125℃
Number of I/O
16
Number of Supporting Devices
2
Operating Temperature
-40℃~+85℃
Output Current per Pin(Max)
50mA
Output Type
Push-Pull
Quiescent Supply Current
1uA
Standby Current
1.5uA
Voltage - Supply
1.65V~5.5V
Voltage - Supply(Absolute Max)
6.5V

Order codes

1

Pinout

25
The pins of the PCAL6416AHF
PinNameType
1P0_0Input/output
2P0_1Input/output
3P0_2Input/output
4P0_3Input/output
5P0_4Input/output
6P0_5Input/output
7P0_6Input/output
8P0_7Input/output
9V_{SS}Power in
10P1_0Input/output
11P1_1Input/output
12P1_2Input/output
13P1_3Input/output
14P1_4Input/output
15P1_5Input/output
16P1_6Input/output
17P1_7Input/output
18ADDRInput
19SCLInput
20SDAInput/output
21V_{DD(P)}Power in
22INTOpen collector
23V_{DD(I2C-bus)}Power in
24RESETInput
25EPPassive

Open-source boards using it

All 8
  • 4 layers106 × 80 mmMainboard, the printed circuit board in 3D

    Mainboard

    PyroVision-ThermalCam/Mainboard

    Mainboard for the PyroVision thermal camera.

    152 parts11GPL-3.0
  • 2 layers70.6 × 53.3 mmJasmine, the printed circuit board in 3D

    Jasmine

    greatfet-hardware/jasmine

    a lithium polymer battery charging neighbor

    93 parts4BSD-3-Clause
  • 2 layers106 × 80 mmDisplayboard, the printed circuit board in 3D

    Displayboard

    PyroVision-ThermalCam/Displayboard

    Displayboard for the PyroVision thermal camera.

    27 parts4GPL-3.0
  • 4 layers130 × 51 mmAlpakka, the printed circuit board in 3D

    Alpakka

    hlord2000/alpakka_pcb

    53 parts2
  • 4 layers184.3 × 131 mmPortaPi R1, the printed circuit board in 3D

    PortaPi R1

    JakeBoothy/PortaPi

    A portable Raspberry Pi Zero W2

    199 parts
  • 2 layers101.6 × 101.6 mmAndromeda, the printed circuit board in 3D

    Andromeda

    ncarpenedo/AndromedaPCB

    109 parts
  • 2 layers104.4 × 15 mmNref trackpad, the printed circuit board in 3D

    Nref trackpad

    cetola/reform-next-mirror

    The original Open Hardware laptop, reloaded.

    14 parts

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Questions

Is there a KiCad symbol and footprint for the PCAL6416AHF?

Yes. The symbol is Interface_Expansion:PCAL6416AHF and the footprint Package_DFN_QFN:HVQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm, both drawn on this page. PCBKit places them on a board for you when you design with it.

What package is the PCAL6416AHF?

HWQFN-24, with 25 pins. Its footprint is drawn on this page.

Where is the PCAL6416AHF datasheet?

NXP Semiconductors publishes it: the Datasheet link on this page opens it.

Where can I order the PCAL6416AHF?

JLCPCB lists it as part C2652287, with 9,748 in stock; the sellers' links on this page open their listings.

What can replace the PCAL6416AHF?

Parts like it in the library: the PCA9555PW by NXP Semiconductors, the AW9523BTQR by AWINIC, the TCA6416ARTWR by Texas Instruments and the TCA9535PW by Texas Instruments. Check their datasheets: a part that fits the footprint may still differ in its ratings.

Which open-source boards use the PCAL6416AHF?

8 boards in 8 repositories on GitHub; the most starred are listed on this page, with their KiCad files.

Parts like it

8