Xc2064-mega shield

prjfreeman: the Xilinx XC2064 in yosys and nextpnr

The XC2064 (1985) was the first FPGA: 64 Configurable Logic Blocks (CLBs) in an 8×8 grid and 58 I/O pins. This repo models it as a nextpnr Himbächel uarch with a yosys plugin, so that Verilog designs can be synthesized, placed and routed for the original chip and turned into a bitstream in the format of Xilinx's XACT, all with an open-source flow.

[!WARNING] Not tested on real hardware. None of the generated bitstreams has been loaded onto a real XC2064 yet. For 44 test runs, MAKEBITS from Xilinx's XACT produces bit-identical bitstreams from the same placement and routing, but the clock buffer codes come from XACT's model, and the edge of the IOB flip-flop and Shirriff's K mux codes have not been checked on a chip. See Open items.

What it can do

• Synthesis: the yosys plugin synth_xc2064 maps Verilog onto the function generators of the CLBs (3- and 4-input LUTs, the FGM mux mode), flip-flops and latches with asynchronous set/reset, latched inputs in the IOB and tristate or bidirectional pads.
• Place & route: a routing graph built from the real configuration bits (switch matrices, PIPs, single-length segments, Long Lines, the clock buffers GCLK and ACLK, repowering buffers), an exact legality check of every CLB, and timing for the speed grades -50 to -130 from the Xilinx Data Books.
• Packages: PC68, PD48, PC44 and PG68, pins constrained with a PCF file.
• GUI: a schematic of the whole chip with all lines, Bels and pips, in which every routed path can be followed from the pad to the flip-flop.
• Bitstream: xc2064pack writes RBT and BIT files in XACT's format; xc2064unpack and xc2064netlist turn a bitstream back into readable text and into a netlist.
• Verification: a regression test proves every result formally equivalent to the RTL (after routing, from the used pips alone and from the bitstream) and cross-checks the bitstreams with Ken Shirriff's independent decoder and with XACT.

Quick start

This repo lives as arch/xc2064 in the repo that builds yosys and nextpnr (scripts/build-nextpnr.sh); the commands run from that repo's root:

git clone --recurse-submodules https://github.com/swittlich/prjfreeman arch/xc2064
scripts/build-nextpnr.sh debug     # nextpnr with the xc2064 uarch
arch/xc2064/flow.sh --gui          # synthesize examples/blinky.v, then Pack, Place, Route in the GUI
arch/xc2064/test/run.sh            # regression test over all examples

Documentation

Contributing

Contributions are welcome: bug reports, questions, improvements to the model, the tools or the documentation, and above all anyone who can try a bitstream on a real XC2064. Please open an issue or a pull request on GitHub. Before submitting changes to the model or the tools, run arch/xc2064/test/run.sh (every run must pass) and, for the bitstream tools, arch/xc2064/test/bitstreams.sh. Contributions are accepted under the same license as the project (ISC, see License).

Acknowledgements

This work builds on Ken Shirriff's reverse engineering of the XC2064 (blog post, shirriff/xc2064), the XACT bitstreams in rates37/openxc2064 and the Xilinx Data Books. All references are listed in Data sources.

License

Copyright (C) 2026 Sebastian Wittlich

This project is licensed under the ISC License, the same permissive license as yosys and nextpnr. In short: you may use, copy, change and distribute it, also commercially and as part of closed source, as long as the copyright notice and the permission notice are kept. It comes without any warranty.

The submodules in external/ keep their own licenses. Your own designs and the netlists and bitstreams the tools generate from them are not affected by the license of this project.