

Debug board
Monorepo for all schematics and PCB designs
- Size
- 65 × 59.5 mm
- Copper layers
- 2
- Thickness
- 1.6 mm
- Parts
- 53
- Nets
- 54
- Pads
- 181
- Tracks, vias
- 271, 21
- Pours
- 1
- Routed
- Yes
- KiCad
- KiCad 8.0 (file 20240108)
- Created
- 4 Oct 2022
- Updated
- 6 Aug 2026
Overview
Debug board is an open-source printed circuit board by sufst, from the sufst/pcb repository on GitHub, published under the GPL-3.0 licence. It is a 2-layer board of 65 × 59.5 mm with 53 parts on 54 nets, routed with 271 tracks and 21 vias.
It is built around the PIC18F47Q84-I/PT, MAX3051ESA+ and AZ1117CH-3.3TRG1, with the T0603FF0250TM among its other parts. Its parts include 18 resistors, 10 connectors, 9 capacitors, 4 diodes and 3 ICs. It belongs with the PIC boards of this library.
Main components
4PIC18F47Q84-I/PT
TQFP-44(10x10)-40℃~+85℃ 1.8V~5.5V 128KB 12bit 1KB 36 64MHz 8 Bit 8KB 8bit Built-in FLASH PIC TQFP-44(10x10) Microcontrollers (MCU/MPU/SOC) ROHSMicrochip TechnologyMicrocontrollers (MCU/MPU/SOC)MAX3051ESA+
SOIC-8-40℃~+85℃ 1Mbps 3.14V~3.47V 35mA 8uA CAN Transceiver SOIC-8 CAN Transceivers ROHSMaxim Integrated (Analog Devices)CAN TransceiversAZ1117CH-3.3TRG1
SOT-223-20℃~+125℃@(Tj) 0.003%Vout 1 1.2V@(800mA) 1.35A 10V 3.3V 4mA 70dB@(120Hz) Fixed Over Current Protection、Over Temperature Protection Positive SOT-223 Voltage Regulators - Linear, Low Drop Out (LDO) Regulators ROHSDiodes IncorporatedVoltage Regulators - Linear, Low Drop Out (LDO) RegulatorsT0603FF0250TM
0603UncategorisedAEM
README
README.mdPCBs
About
Central repository of all schematics and PCB design files.
| Folder | Project | Project Code |
|---|---|---|
| ail | Accumulator Indicator Light Logic | ail |
| ail-led | Accumulator Indicator Light Led | ail-led |
| batak | Batak Game (non-car) | batak |
| break-light | Rear Break Light | break-light |
| bspd | Brake System Plausibility Device | bspd |
| can-node | Voltage Reader and Broadcaster | can-node |
| curr-amp | Current Sensor Amplifier | curr-amp |
| dash | Dashboard | dash |
| discharge | Discharge Relay Breakout | discharge |
| hv-sense | High Voltage Sense | hvs |
| latching | Latch Circuit | latching |
| loom* | Loom Design | loom |
| lvbms | Low Voltage Battery Management System | lvbms |
| precharge | Precharge Controller | precharge |
| segment | Segment | segment |
| telemetry | On-Car Telemetry | telemetry |
| test-rig | PCB Test / Demo Rig | test |
| top-level* | Full Car Schematic | |
| trc | TSAC Relay Controller | trc |
| tsal | Tractive System Active Light | tsal |
| vcu | Vehicle Control Unit | vcu |
We design our PCBs in KiCad (version 8+).
*Moved to https://github.com/sufst/loom
Version Control for KiCad Projects
Why?
- Revert individual changes.
- Document development history via commits and GitHub issues.
- Easily view previous versions of designs.
- Manage shared library of components.
Files
Files that should be in this repo, under version control:
- Project files (
.kicad_pro). - Schematic files (
.kicad_sch). - PCB files (
.kicad_pcb). - Custom footprints (
.kicad_mod). - Custom symbols (
.kicad_sym). - Footprint library tables (
fp-lib-table). - Symbol library tables (
sym-lib-table). - 3D models of components (
.stepfiles). - Simulation code (e.g.
.ascfiles from LTSpice).
Files that should never be in here:
- Exports such as BOMs, gerbers, netlists, renders, etc.
- Local project settings (
.kicad_prl). - Project backups (.zip files generated in
<project name>-backups,.bak.bck-bakfiles). - Cache files (
fp-info-cache).
The .gitignore should prevent the addition of files we don't want to keep in here, but before you commit make sure to do a quick check of what is actually being added.
Shared Resources
The common folder is used for resources which can be shared across multiple projects. This includes:
- Images (
imagessubdirectory). - 3D models (
stepsubdirectory). - Custom symbols (
sufst-lib.kicad_sym). - Custom footprints (
sufst-lib.pretty). - SUFST standard sheet layout (
sheet-layout.kicad_wks).
Note: Since projects were previously in their own individual repos, many designs still have their own libraries, step files, etc. These will gradually be migrated to the SUFST library.
Library Paths
When you configure the library paths for a project (sym-lib-table and fp-lib-table data), make sure to always use a path relative to the project with the ${KIPRJMOD} substitution.
- Correct:
${KIPRJMOD}/../common/sufst-lib.kicad_sym - Incorrect:
/Users/<your name>/Documents/sufst/pcb/common/sufst-lib.kicad_sym
If an absolute path is used, when someone else opens the project that path will not exist and the library paths will not be valid. -lib-table files should never contain an absolute path.
Git Limitations
It is not possible to resolve merge conflicts within individual design files, which is an unfortunate limitation of using git with KiCad. While KiCad files are in a text format, they aren't really designed to be edited manually. It is therefore essential that only one person is editing a particular file in a project at a time (including the shared library). Once someone starts working on a file, until it is merged into the main branch nobody else can edit that file. A good way to get round this is to use the "hierarchical sheets" feature to divide schematics into multiple files (if it can be done in a logical way).
Releases
Release Files
When a PCB is fabricated, a new 'release' for the given project should be
created and stored within this repo in the releases/<PROJECT NAME> folder.
This folder should contain the latest version (and ONLY the latest version) of
the following files:
- Exported gerbers and drill files in a ZIP archive called
fabrication.zip. - Schematic sheets as a PDF (
Schematic.pdf). - Layout as a PDF in colour, with border and title block (
Layout.pdf). - HTML iBOM created using the "Interactive HTML BOM Plugin" (
ibom.html).
Additionally, a file called info (no extension) should be created (if it
doesn't already exist) containing release information in the following format:
version: <VERSION NUMBER>
date: <RELEASE DATE>
fabrication: <COMPANY>Version numbers should be in the format v1.0.1 and dates should be in the
format YYYY-MM-DD. For example:
version: v1.0.1
date: 2023-01-23
fabrication: JLCPCBThe release folder for a project should then have the following structure and file names:
<PROJECT NAME>
├── Layout.pdf
├── Schematic.pdf
├── fabrication.zip
├── ibom.html
└── infoWhen creating a new release, make sure to overwrite/replace all the existing files.
Release Tag
The release commit should then be tagged with the following command:
git tag <PROJECT CODE>-<VERSION_NUMBER>Tagging should be done after merging to main! Example command:
git tag segment-v1.0.1To push tags to GitHub:
git push --tagsParts
53| Qty | Value | Footprint | References |
|---|---|---|---|
| 8 | Conn_01x02_Pin | Connector_Molex:Molex_Micro-Fit_3.0_43045-0200_2x01_P3.00mm_Horizontal | J1, J2, J3, J5, J6, J8, J9, J10 |
| 7 | 10k | Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder | R1, R8, R10, R11, R14, R16, R18 |
| 4 | 0 | Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder | R3, R4, R5, R6 |
| 4 | 40k | Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder | R7, R9, R15, R17 |
| 4 | BZT585B3V3T-7 | Diode_SMD:D_SOD-523 | D1, D2, D3, D4 |
| 3 | 100n | Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder | C1, C2, C8 |
| 3 | 10u | Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder | C3, C4, C10 |
| 2 | 10p | Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder | C5, C6 |
| 2 | 60R | Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder | R12, R13 |
| 2 | T0603FF0250TM | Fuse:Fuse_0603_1608Metric_Pad1.05x0.95mm_HandSolder | F1, F2 |
| 1 | 12 | Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder | R2 |
| 1 | 40MHz | Crystal:Crystal_SMD_SeikoEpson_FA128-4Pin_2.0x1.6mm | Y1 |
| 1 | 4n7 | Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder | C9 |
| 1 | AZ1117CH-3.3TRG1 | Package_TO_SOT_SMD:SOT-223-3_TabPin2 | U2 |
| 1 | Conn_01x02_Pin | sufst-lib:Conn2_SMD | J7 |
| 1 | Conn_01x05_Pin | Connector_PinSocket_2.54mm:PinSocket_1x05_P2.54mm_Horizontal | J4 |
| 1 | MAX3051ESA+ | Package_SO:SOIC-8_3.9x4.9mm_P1.27mm | U3 |
| 1 | PIC18F47Q84-I/PT | Package_QFP:TQFP-44_10x10mm_P0.8mm | U1 |
The 47 most common of 53 parts.
Questions
How big is the Debug board PCB?
It measures 65 × 59.5 mm and has 2 copper layers, 1.6 mm thick.
What parts does the Debug board use?
53 parts, built around the PIC18F47Q84-I/PT, MAX3051ESA+, AZ1117CH-3.3TRG1 and T0603FF0250TM. The full list of its parts is on this page, with links to each part's symbol and footprint where PCBKit's library has them.
Where can I download the Debug board KiCad files?
From the sufst/pcb repository on GitHub, at the commit this page was made from: the board is archive/debug-board/debug-board.kicad_pcb. PCBKit opens the board in the browser, with nothing to install.
Can I use the Debug board design in my own project?
Its repository publishes it under the GPL-3.0 licence: you may reuse it on that licence's terms (keep the author's notice, and for a copyleft licence share your changes alike).
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