Module board

STASIS — 512-Core CH32V003 RISC-V Compute Cluster

A massively parallel, modular RISC-V compute cluster built from 512 CH32V003 microcontrollers, designed for neural network inference, extremely slow graphics rendering, and embarrassingly parallel workloads.

Overview

CH32V003512 is a custom compute cluster built entirely from WCH CH32V003 RISC-V microcontrollers. 512 worker cores are organized across 32 hot-swappable modules, connected via a hierarchical SPI fabric to a host MCU that interfaces with a PC over USB. The system is designed for parallel workloads including neural network inference, raytracing, cellular automata, and any embarrassingly parallel computation.

I created this project inspired by bitluni's lab take on a ch32v003 cluster. The architecture was inspired by my prior knowledge of chip design. My goal is to emulate tiny distributed computing in an easy to understand way.

This project was built for Hack Club Stasis.

Architecture

PC (USB/Serial)
└── Host MCU — CH32V307 (USB-HS)
    └── SPI Bus
        ├── Column Controller 0 — CH32V307
        │   ├── PSU (5V → 3.3V, ~5A)
        │   └── Slot Router ×8 — CH32V203
        │       └── 16× CH32V003 Worker Cores (via SPI ring)
        ├── Column Controller 1 — CH32V307
        ├── Column Controller 2 — CH32V307
        └── Column Controller 3 — CH32V307

MCU Roles

Hardware

System Boards

NOTE: May need 2 seperate programmer boards for columns and compute modules, because they don't follow the same pin layout.

Module Board

• Size: M.2 2260 (22×60mm), 4-layer PCB
• Workers: 16× CH32V003J4M6 in QFN-20 (3×3mm each)
• Interface: M.2 Key B, 0.5mm pin pitch
• LEDs: 16× green per-worker activity + 4× status (power, SPI, reset, ready)
• Topology: SPI daisy-chain ring, slot router as master

Backplane

• Columns: 4× removable column boards via M.2 Key A/E connector
• Power: ATX PSU input, per-column regulation
• Host MCU: CH32V307 with USB-HS
• LEDs: Per-slot status (128), per-column status (20), system status bank (20)
• Hot-swap: Per-slot AP2141 load switch, soft-eject protocol

M.2 Module Pinout (Key B, 75 pins)

SWD is handled entirely on the backplane by the CH32V203 slot router.
No SWD signals cross the M.2 connector during normal operation.

LED Map

Software / SDK

A custom SDK is being developed targeting all tiers of the hierarchy: It will be a combination of a custom compiler, communications package and flasher, and will have a 80-120 instruction set for programming the workers. The compiler will generate the code into arduino .INO files, the flasher will autonomously flash the worker and column modules. The communications package is in charge of talking to the main MCU using Serial via USB. It is a very heavy SDK for a very heavy board. The board will probably weight like 5 pounds.

Workload Model

Jobs are tiled into small packets (<512 bytes) to fit within router SRAM constraints. The host PC dispatches job tiles down the hierarchy:

PC -> Host MCU -> Column Controller -> Slot Router -> Worker Core
                                                  |
PC <- Host MCU <- Column Controller <- Slot Router <- Result

BOM Summary

Project Status

• System architecture defined
• MCU selection finalized
• M.2 pinout spec complete
• LED strategy defined
• KiCad schematic — top level hierarchy
• KiCad schematic — module board
• [ x KiCad schematic — backplane
• [WIP] KiCad schematic — column board
• KiCad schematic — programmer board
• PCB layout — module board
• PCB layout — backplane
• PCB layout — column board
• Bring-up and testing
• SDK — worker firmware
• SDK — router/controller firmware
• SDK — PC interface
• Compute kernels

Tools & Fabrication

• EDA: KiCad 9
• PCB Fab: JLCPCB (4-layer and 2-layer, PCBA)
• Programming: Custom programmer board (separate project)
• Languages: C (firmware), Python / C++ / Rust (host SDK)

Inspiration

Heavily inspired by bitluni's CH32V003 cluster. STASIS scales the concept to 512 cores with a structured hierarchical fabric, hot-swap modules, custom tooling, and a full SDK.

License

MIT License — see LICENSE for details.

Author

Built for Hack Club Stasis.
If you're reading this and you've also built something unhinged out of cheap RISC-V chips, let's talk.