Smove r2-main

Main PCB — 25 × 30 × 1 mm manual-layout reset

Current schematic ECO — pack cutoff switch, charger status, 3V3 LDO (2026-09-15, SCHEMATIC ONLY)

Applied to power.kicad_sch, compute.kicad_sch and smove-r2-main.kicad_sch:

• SW1 — hard pack cutoff. An off-board toggle switch in series in the battery + lead, upstream of the PACK_P node. Schematic symbol uses the same 2.54 mm two-pad wire footprint as J2 (smove-r2-main:BatteryWire_2x_PTH_P2.54mm_D1.0mm), in_bom no (user-supplied off-board part: ≥0.5 A rating, contacts <50 mΩ, ≥6 V DC). Net split: /Power/PACK_RAW = J2.1 + SW1.2, /Power/PACK_P = SW1.1 + C2.1 + R14.1 + U6.2 + U6.3. This provides the True OFF that docs/revision-r2/integrated/RADIO-BATTERY.md records as missing.
• R24 (100k, LCSC C25741) + /CHG_N net — charger status to the MCU. Charger open-drain CHG_N (U6 pin 9) is pulled up to 3V3_MAIN and routed to U1 pad 20 = GPIO6; /CHG_N = U6.9 + R24.2 + U1.20. New sheet pin added to both the Power and Compute sheet symbols.
• U4 = XC6220B331MR-G (Torex, LCSC C86534) replaces AP2112K-3.3TRG1. The SOT-25 pin map 1=VIN 2=VSS 3=CE 4=NC 5=VOUT is the same function map as the AP2112K SOT-23-5 it replaces, so no rewire and no pad remap was needed. New footprint assets/smove-r2-main.pretty/SOT-25_XC6220.kicad_mod (JEDEC MO-178 Var AA land pattern, identical geometry to SOT-23-5); the SW1 symbol was added to assets/smove-r2-main.kicad_sym.
• J2 was moved down 10.16 mm on the sheet only (cosmetic, no connectivity change) to make room for SW1.

Verification (KiCad 9.0.8): kicad-cli sch erc reports 0 violations — identical to the HEAD baseline, and kicad-cli sch export netlist confirms the three nets above.

Deliberately not done — no PCB change and no routing. The board still carries the AP2112K SOT-23-5 at U4 (its footprint field now differs from the schematic) and has no SW1/R24 footprints, so a forward update (F8) plus manual placement is required before parity is restored. dist/ and the enclosure data remain stale and must be regenerated (python3 scripts/jlcpcb/export.py PCB/main --overwrite) after the board is updated. Engineering prototype — no charge or fabrication approval.

Library and asset layout

All project-local KiCad libraries and models now live under assets/ (moved from the project root; content byte-identical apart from the references below):

fp-lib-table/sym-lib-table stay at the project root and point at ${KIPRJMOD}/assets/.... Schematic sheets, project/design-rule files and dist/ are untouched; only the U2 3D-model path (in the board and in assets/imu.pretty/InvenSense_QFN-24_3x3mm_P0.4mm.kicad_mod) changed text.

Verified with KiCad 9.0.8: the board reloads with the same 47 footprints, 461 tracks and 7 zones; DRC reports 0 violations / 0 unconnected / 0 schematic-parity (the DRC library check covers footprint-library resolution), ERC reports 0 violations, and all four symbol libraries parse and still contain every referenced symbol. Historical ECO scripts under scripts/r2/ (for example integrated/migrate.py, integrated/layout.py) still name the pre-move project-root paths; they are documented as destructive historical helpers and must not be rerun on this board.

Status note: the headings below describe earlier working states. DRC on the currently saved smove-r2-main.kicad_pcb reports 0 violations, 0 unconnected items and 0 schematic-parity issues, and no footprint origin lies outside the board outline, so the "UNROUTED / components staged" wording below is stale and has not been rewritten here.

M3 screw mounting holes with grounded copper rings (2026-09-15)

Three plated 3.2 mm M3 clearance holes were added to the three free board corners, each with a 5.0 mm grounded copper ring on all four copper layers:

• Each centre is exactly 3.20 mm in from both adjacent edges, so the three holes are identical except for the corner they avoid. The top-right corner is occupied by J2 and R3/R4/U8 — 1.4 mm of clear width, less than the drill.
• Footprint smove-r2-main:MountingHole_3.2mm_M3_Pad_5mm lives in assets/smove-r2-main.pretty/. It is a reduced-ring variant of KiCad's MountingHole:MountingHole_3.2mm_M3_Pad: that part's 6.4 mm pad needs 3.45 mm of board-edge clearance and does not fit any corner of this board. 5.0 mm is the largest ring that keeps ≥0.25 mm copper-to-edge (actual 0.70 mm), ≥0.15 mm foreign-net clearance (actual 0.44/1.10/0.81 mm) and a non-overlapping courtyard (actual 0.26/0.41/0.33 mm, courtyard = the 5.5 mm M3 head envelope) at all three positions.
• board_only, excluded from BOM and position files, no schematic symbol: mounting hardware is not a purchased or placed part, and schematic parity stays 0.
• Zones were deliberately not refilled. The rings join the GND node by overlapping the saved In1.Cu plane (all three centres are inside the fill, DRC 0 unconnected). A fresh refill would re-cut 31.6 mm² of that plane even on the unmodified board, which is not part of this change.
• Board diff is +333 lines, 0 deletions; deleting the three footprint blocks reproduces the previous board byte-for-byte. bom.csv and pick_and_place.csv are byte-identical; the Gerbers gain only the three 5.0 mm rings and their mask openings, and the PTH drill gains one T4C3.200 tool with three hits.
• DRC 0 / 0 / 0, ERC 0. See the change record and its verification.json; reproduce with python3 scripts/r2/final/m3_mounting_holes.py --check --geometry and python3 scripts/r2/m3-mounting-holes/verify.py.
• The enclosure does not have these holes. housing/ is still the screwless revision (no bosses, threads or inserts); it needs a companion revision before M3 hardware is usable. Physical fit, torque and the RF effect of the new metal near the ESP32-C3 antenna are unqualified.

Silkscreen outlines, pin-1 markers and free-library parts (2026-09-15)

All 46 assembled parts still carry verified LCSC+MPN fields, and the export (python3 scripts/jlcpcb/export.py PCB/main) now also reflects these changes; see the change record and its verification.json, renders and live BOM audit.

• U6 (BQ24074RGTR) had no silkscreen, so it had no pin-1 indicator: three corner brackets plus the same outside pin-1 arrowhead the IMU (U2) uses now point at the TS/pad-1 corner.
• U1 (ESP32-C3-MINI-1) body outline and antenna boundary existed only on F.Fab. F.Fab is not part of the Gerber set, so JLCPCB's placement preview showed the module as bare 0.4 mm pads — that is why it "did not line up" there. The body outline is now copied to F.SilkS, clipped at the 100.0 mm board edge where the module overhangs, and the F.Fab corner chamfer is deliberately not copied (it crosses the left anchor pad).
• J1 (USB-C receptacle) had no silkscreen at all — the standard shell lines were on F.Fab — so the same problem applied. Its shell sides and pad-side end are now on F.SilkS, offset past the S1 shell pads and clipped at the board-edge notch.
• D1 (LTST-C19HE1WT) got a closed silkscreen outline outside the land pattern with a gap over the pad-1 corner.
• The same geometry was added to the project-local library footprints (assets/smove-r2-main.pretty/*.kicad_mod), so the DRC library check stays clean.
• C3 moved from C29277 (22 µF 10 V, Extended, $3 setup fee) to C45783 (22 µF 25 V X5R 0805, Basic). Every other resistor and capacitor is already Basic/Preferred Extended and therefore fee-free, including R21 (C25924); the estimated extended-part fee drops from $33.00 to $30.00, and the remaining charge is the ten design-fixed actives.

Verification: DRC 0 violations / 0 unconnected / 0 schematic-parity, ERC 0, added silk keeps ≥0.17 mm to the nearest pad (board rule 0.10 mm), F_Silkscreen.gto gains 36 draw commands, bom.csv differs only in the C3 row and pick_and_place.csv is byte-identical. C45783's pocket-height check and a fresh DC-bias screen are still open.

JLCPCB fabrication and assembly export

/usr/bin/python3 scripts/jlcpcb/export.py PCB/main (add --overwrite to refresh an existing set) writes dist/jlcpcb/: gerber.zip (all four copper layers, masks, silkscreen, paste, edge cuts, separate PTH/NPTH millimetre drills), bom.csv, pick_and_place.csv and export-report.json. See the export tool documentation.

• Generated from the currently saved board (47 footprints, 461 tracks, 70 vias, 7 zones, 4 copper layers, aux origin 100/135) at this revision. Native DRC/parity on that same file reports 0 violations, 0 unconnected items, 0 schematic-parity issues; the export tool re-verifies KiCad's own position output against the board file before writing anything.
• All 46 assembled parts carry a JLCPCB/LCSC catalogue number in the native LCSC field, together with MPN, on both the schematic symbols and the board footprints. The verified numbers are recorded in main-parts.csv and stock.json. J2 (the two plated battery wire holes) is intentionally PCB-only and excluded from both BOM and CPL.
• Engineering export only: not a fabrication, assembly or charging release. The tool does not refill zones, run DRC/ERC, check supplier stock or qualify any purchase code, and housing/ remains a separate historical snapshot.

Current: schematic links repaired; components staged — UNROUTED

All 47 schematic footprints are now present. U1 (ESP32), J1 (USB-C), U2 (IMU), and J2 (battery +/− holes) retain their poses and geometry. The other 43 footprints are staged outside the board to the right for manual placement. No tracks or vias were added.

The reported dialog was Update Schematic from PCB, the reverse direction. Use Tools → Update PCB from Schematic (F8) to bring schematic components into the board. The four old footprint paths also contained an extra root-sheet UUID; one reference-based re-link repaired them without replacing or moving the footprints. Re-link is now off for normal updates. A repeat forward-update preview reports 0 errors and 0 warnings, without duplicate additions. KiCad also repaired duplicate pad UUIDs on save; all pad geometry/nets and footprint UUIDs remain unchanged.

Update verification: 0 schematic-parity issues, 148 expected unconnected items, and one pre-existing J2/U1 courtyard overlap, left unchanged to preserve both fixed positions. Schematics and design rules on disk are unchanged. The latest saved zone state was preserved: five rule areas and one filled In1 GND plane; the earlier six-unfilled-zone reset below is historical. Not for manufacture or charging; exports remain stale.

Historical: manual placement/routing reset — UNROUTED

Only U1 (ESP32), J1 (USB-C), U2 (IMU), and J2 (battery +/− through-hole pads) remain in the PCB layout, with their complete footprint definitions, positions, orientations and pad/net assignments unchanged. The other 43 footprints were deleted from the PCB only; all schematic sheets and project/rule files remain unchanged.

Removed 500 track segments, 124 vias, and all 38 cached copper-fill polygons. All six copper-zone definitions are retained unfilled, including In1 GND and the In2 GND / 3V3_MAIN / PACK_P regions. Board outline, stackup, drawings and all keepouts are unchanged. This is actual copper removal, not merely hidden pours.

Verification: exact-token preservation check and native board load pass; native DRC reports 0 geometric violations, 45 intentionally unconnected items, and 43 expected missing-footprint parity warnings, plus the existing J2 library-footprint mismatch warning. Previous routed-board acceptance scripts/reports below are historical and are not acceptance criteria for this reset. Not for fabrication/assembly/charging; existing exports and enclosure placement data are stale.

For manual placement, open smove-r2-main.kicad_pro in KiCad and use Update PCB from Schematic (F8) when ready to re-add the missing footprints. Do not delete their schematic symbols. The standalone PCB Editor has this command disabled; launch the editors through the project. J2 was restored verbatim from the pre-reset board at the user’s request, retaining both battery +/− holes. The other 43 missing components have not been re-added or parked outside the board.

Historical: routed review candidate

See the routing completion and plane-selection evidence. The user's rotated-U8 USB routing is preserved, remaining nets are connected on F.Cu/B.Cu, In1 is continuous GND, and In2 has bounded 3V3_MAIN / PACK_P power regions with GND elsewhere. C7 alone is rotated 180° to fix its isolated ground connection; other placements, pad nets and keepouts are unchanged.

Fresh native checks: 0 DRC errors, 0 unconnected items, 0 schematic-parity issues, 0 ERC violations; one existing J2 footprint-library warning. Reusable coordinate routing, via placement, rotation previews, explicit rip-up and cleanup tools are documented in scripts/pcb_tools. Run /usr/bin/python3 scripts/r2/main-routing/verify.py for current acceptance checks.

Not released for fabrication or charging. USB impedance, current/thermal margins and return paths still need engineering review. Some low-speed paths take long perimeter detours. dist/ and the enclosure are stale; no manufacturing exports were regenerated.

Historical: grouped placement review — UNROUTED

See the placement revision and researched routing strategy. U1, USB, battery pads, outline and both M3 reserved positions are unchanged. The LED/buttons are upper-left, charger/regulator parts are together beside USB, and U2 remains at X112.5 with its original orientation, now at Y126.5. RED is reassigned from GPIO6 to GPIO3; GREEN=GPIO7 and BLUE=GPIO10 remain unchanged. Firmware must adopt the RED pin change.

Placement only: 152 unconnected items; zero tracks/vias. Obsolete routing was removed deliberately, not left connecting the wrong pads. Current zone definitions are retained but unfilled; the researched power-region strategy is not implemented yet. Placement geometry, ERC and schematic parity pass, with the existing J2 library-footprint warning. This is not a finished reroute or manufacturing/charging release. Existing dist/ and enclosure openings are stale.

Run /usr/bin/python3 scripts/r2/placement-routing/review.py for this revision's checks. Do not use the historical LED-only verifier or layout generators as current acceptance tests.

Historical: LED routed on the previous layout

The LED routing update builds on the user's b155f03 routing setup. All RGB channels are connected, with D1 and every other footprint left in place. Top-left and bottom-right 6 mm clear disks are protected for future M3 hardware; no mounting holes were added. Fresh checks report 0 DRC errors, 0 unconnected items, 0 schematic-parity issues, with three unchanged pre-existing warnings.

The native PCB is authoritative. dist/ and the enclosure are older snapshots, not regenerated for this routing update. Do not use the older manufacturing bundle without regeneration and review. Run scripts/r2/main/verify_led_routing.py for current checks; do not run historical layout generators over this board.

Historical screwless revision (before the user's reroute)

Current: screwless revision. Not released for manufacture, assembly or charging.

• Removed the H1 3.2 mm NPTH footprint and its H1-specific copper exclusion. Refilled copper zones into the reclaimed region; did not reroute or run legacy routing generators. Clean configured DRC/connectivity/parity did not require disturbing the accepted routing.
• Exact token comparisons retain all 1,726 segments, 97 vias, 47 non-H1 footprints and pad/net/placement data, board outline, layer/setup data and antenna/corner rules. All five schematics, project rules and electrical parts are unchanged. Existing corner copper-free regions remain dielectric contact reserves, not fastener mounting features.
• Fresh configured ERC / DRC / unconnected / schematic-parity counts: zero. Existing ignored defaults remain unchanged; this is not electrical or charging release.
• Four layers, 1 mm nominal total board; In1 GND reference and existing circuit retained. Integrated top IMU +Z outward, underside toward body. Aligned RESET/BOOT at native X121.25; no new UART/testpoints/connectors.
• BAT+ native (104.5,105.57), BAT− (104.5,103.03); 2.54 mm pitch, 1 mm drill target, 2 mm pads unchanged. USB's two 0.65 mm component locating NPTH holes and plated connector/BAT holes remain: these belong to the preserved electrical connector footprint, not enclosure mounting hardware. No enclosure mounting holes remain.
• dist/ is regenerated for this native PCB: Gerbers/drills, BOM/CPL, assembly PDF, board/installed-model STEP and renders. Conservative populated STEP uses exactly one instance per reference, no duplicate display copies. Missing vendor models remain limitations of installed-model renders.
• PCB-only STEP uses drill origin (100,135), unlike housing Y=139−nativeY. Its 0.91 mm dielectric thickness omits copper; the housing conservatively reserves the accepted total 1 mm. Do not mistake this export convention for a board-thickness ECO.

The native board is authoritative. Do not run legacy routing or historical sync tools over it. scripts/r2/screwless/pcb.py is the targeted, idempotent ECO/check entry; scripts/r2/screwless/verify.py compares against recorded aligned predecessor b8f2836ac2fb26fc0bf774b803c6613a79e66f1b. The enclosure uses insulated lands, optional adhesive and travel stops, not PCB or pouch clamping. Physical support/fit still needs qualification.

Historical PCB repair and button alignment retain their original scope. Current exports are indexed by dist/manifest.json.