W5500 Board

Programmatic Code-to-PCB: Galvanically Isolated SPI-to-Ethernet Telemetry Node

An automated, programmatically designed, placed, and routed High-Speed Galvanically Isolated Telemetry Node in KiCad 10.0. This repository showcases the "What You See Is What You Code" (WYSIWYC) approach to hardware design, representing schematics and layout designs as clean, version-controlled Python scripts.

🚀 System Architecture & Pipeline

The automated toolchain shifts hardware design from manual GUI layout to versioned, executable code:

⚡ Electrical Diagram

The telemetry node bridges local SPI communications to a Wiznet W5500 Ethernet controller across a galvanically isolated barrier (8mm creepage and clearance gap) with separate power domains and ground planes.

graph TD
    subgraph Host Domain ["Host System Domain (Non-Isolated)"]
        J2[2x5 Pin Host Header] -->|VCC_5V| U5[Host LDO: AMS1117-3.3]
        U5 -->|VCC_3V3| U3_A[Si8641 Side A]
        U5 -->|VCC_3V3| U4_A[Si8642 Side A]
        J2 -->|SPI_HOST| U3_A
        J2 -->|RST/INT_HOST| U4_A
        GND[GND Plane]
    end

    subgraph Isolation Barrier ["8mm creepage & clearance gap"]
        U3_A -.-|Galvanic Isolation| U3_B[Si8641 Side B]
        U4_A -.-|Galvanic Isolation| U4_B[Si8642 Side B]
        U1[DC-DC: Mornsun B0505S-1WR3] -.-|Power Isolation| U1_Out[Isolated 5V]
    end

    subgraph Isolated Domain ["Network Domain (Isolated)"]
        U1_Out -->|ISO_5V| U6[Isolated LDO: AMS1117-3.3]
        U6 -->|ISO_3V3| U3_B
        U6 -->|ISO_3V3| U4_B
        U6 -->|ISO_3V3| U2[W5500 Ethernet Controller]
        U3_B -->|SPI_ISO| U2
        U4_B -->|RST/INT_ISO| U2
        U2 -->|Differential PHY| J1[Hanrun HR911105A MagJack]

🛠️ Layout & Placement Rules

Programmatic Bypass Capacitor Proximity (1.5mm Rule):

High-frequency decoupling capacitors are programmatically clustered within 1.5mm of the target IC power pins using the KiCad 10.0 pcbnew Python API:

• C10, C11, C12, C13, C15, C16: Decouples W5500 supply pins (AVDD / VDD).
• C6, C7, C8, C9: Decouples the digital isolators' supply pins.
• C2, C3, C4, C5: Decouples input/output lines of the host and isolated LDOs.

Programmatic Trace Routing Specs:

1. Differential Ethernet Pairs (F.Cu, 0.3mm / 12 mils): Direct differential traces between W5500 TXP/TXN/RXP/RXN and the Hanrun MagJack.
2. 25MHz Crystal Oscillator Loop (F.Cu, 0.2mm / 8 mils): Minimized-area loop connecting the W5500 XI/XO pins to the Y1 crystal and C21/C22 load capacitors, returning directly to the nearest digital ground pin.
3. Power Routing (F.Cu, 0.5mm / 20 mils): Thick power lines routing 5V/3.3V power rails to support peak current demands.

📦 Manufacturing Packaging & DFM

Running tape_out.py executes the full post-routing workflow:

• Runs Design Rule Checks (DRC).
• Generates Gerber copper/solder mask/silkscreen layers.
• Generates Excellon NC drill files.
• Produces SMD Assembly Placement CSV (positions.csv).
• Packs all deliverables into W5500_Board_Tapeout.zip.

⚡ Quick Start

1. Requirements

• KiCad 10.0.x
• Python 3.10+ with circuit-synth and reportlab (installed inside virtual env)

2. Run the Toolchain

Use KiCad's Python environment to execute the steps:

# 1. Generate schematic and netlist
python generate_board.py

# 2. Run ERC verification and compile reports
python verify_board.py

# 3. Perform component auto-layout and pad matching
python auto_layout.py

# 4. Route differential signals, crystal loops, and power tracks
python route_board.py

# 5. Perform DFM check and generate manufacturing package
python tape_out.py