MSAP-2 rev.A SMD

MSAP-2 hardware exports

The files in this directory are generated from the simulator hardware registry in simulator/src/core/modules.ts. That registry supplies the simulator, pin inspector, power model, netlists, modular PCB layouts, procurement mapping, and monolithic production board.

Development exports

• MSAP-2 rev.A.net — consolidated KiCad netlist for every declared chip, passive, pin, and net.
• MSAP-2 rev.A.kicad_pcb — THT-preferred/hybrid development layout.
• MSAP-2 rev.A SMD.kicad_pcb — SMD-preferred development layout.
• KiCad/ — one standalone KiCad schematic per logical module: POWER_CLOCK_RESET, PROGRAM_COUNTER_14B, A_X_REGISTERS, STACK_POINTER, ALU_FLAGS_IRQ, BOOT_ROM_SHADOW_USER_RAM_16KB, CONTROL_4xAT28C256, UART_SD_TIMER_IO, OUTPUT_7_SEGMENT, ADDRESS_PATH, and BUS.

The two rev.A PCBs are consolidated, two-layer, module-grouped layouts. Their exporter uses simplified generated pad geometry; SMD-only devices remain SMD on the hybrid target. They are unrouted placement/net starters, not exact-footprint, DRC-approved, or routed manufacturing releases. The standalone module sheets use generated symbol boxes and explicit global-label stubs for registry inspection. Each sheet's project suppresses only KiCad's expected isolated_pin_label rule for singleton module-boundary nets; native ERC must otherwise pass with zero findings.

Regenerate them after any hardware-registry change:

cd ../simulator
node scripts/export-schematics.mjs

The simulator's Export menu produces the same files interactively.

Monolithic production board

Production/ contains the special rev.C, full-SMD, six-layer board intended for a PCB assembler. It is a separate target rather than a flattened copy of the development layout.

The production transform:

• retains the 20-package fixed-function ALU;
• uses exact orderable manufacturer part numbers and LCSC/JLC references;
• changes the development ROM implementation to six JLC-assembled Connfly DS1032-32SSKT1LA PLCC-32 sockets (C72280) holding loose, user-installed AT28C256-15JU devices: immutable boot/fallback firmware, four control-store lanes, and the display lookup;
• provides J2 PC / POWER, a CP2102N terminal, a power-off-only PC / STANDALONE selector, a mode-dependent TPS2553 main-current limit followed by a TPS630701 fixed-5 V buck-boost stage, power-good reset, and protected crossings between the always-powered USB domain and regulated 5 V logic;
• adds J7 KEYBOARD HOST with TUSB320LAI attachment detection, TPS2552-1-limited keyboard VBUS, CH9350L USB boot-keyboard decoding, and an ATmega4809 115200-to-9600-baud ASCII bridge; standalone power enters through J2, not J7;
• retains external TTL UART, microSD, UPDI, RUN/STEP/RESET controls, selectable 921.6/460.8/230.4 kHz CPU clocks, test points, the functional LEDs, the port-3 signed/unsigned four-digit display, and protected keyed connectors for one selectable SSD1309 or SSD1306 local OLED;
• uses official KiCad footprints except for project footprints checked against manufacturer drawings;
• creates JLC BOM/CPL files and checks their populated references against the PCB;
• requires a fresh, hash-bound FreeRouting route for rev.C; the checksum-bound rev.B routing/stage-01 data remains historical provenance only;
• emits Gerbers, drills, renders, and the release ZIP only after zero-violation/zero-unconnected KiCad DRC.

Generate the manifest, BOM, programming/assembly-operation list, CP2102N policy, EEPROM images, and deployable MOS.BIN without routing:

cd ../simulator
node scripts/export-production.mjs --source-only

The display lookup is derived from Mux7-Segment, with A8 as the low-order digit bit and A9 as the high-order digit bit. The production image is inverted for the active-low common-anode XL-SB2401SRWC hardware and padded to AT28C256 size.

The six parallel EEPROM images are factory hardware firmware. JLC assembles the sockets, not the EEPROMs. Program and read-back verify the loose devices, keep their reference assignments, and insert them after PCBA delivery with pin 1 aligned to the matching socket/PCB marks; the board has no in-system parallel-EEPROM programming interface. At reset, U36 supplies the immutable bootloader and fallback MOS while writes populate hidden lower shadow SRAM. A validated deployment/MOS.BIN is loaded from microSD, then write-only port 6 exposes that lower shadow as read-only runtime MOS until reset. Missing or invalid media leaves the factory fallback active. User programs and data use the unchanged upper SRAM through the UART monitor or microSD.

The checked-in rev.B route stage does not contain the rev.C keyboard-host circuitry. The current complete release therefore requires KiCad and a completely fresh npm run production with FREEROUTING_COMMAND; use a deterministic finish-stage flow again only after a rev.C route has been frozen and checksum-bound. See Production/README.md for the reproducible release and order procedure.

The exact PCB/BOM/CPL flow is separate from programming readiness. A clean rev.C package may record firstArticleOrder.inputsReady: true for an explicitly approved two-board prototype upload while retaining orderAuthorized: false and turnkeyAssemblyReleaseAllowed: false; physical programming and qualification remain post-delivery gates. The pinned PlatformIO build now produces a real U140 HEX with SHA-256 a0ce14514700d34f87a239f6a3d433811e78247802356a7ebcc51cb7f086390d, and that exact artifact is included in the rev.C release packaging. No programmed ATmega4809 readback exists yet. A deterministic CP2102N prototype policy is also included, but a vendor-generated/device-read-back-verified CP2102N configuration record remains outstanding. U140 provides disk service, OLED output mirroring, and the standalone keyboard bridge, so all three functions belong in its first-article firmware test.

Source-of-truth rule

Do not hand-edit a generated rev.A netlist, PCB, or per-module schematic and expect the change to persist. Make electrical changes in the hardware registry and regenerate. Production-only transformations, exact footprint loading, placement, release validation, and manufacturing exports live under simulator/src/export/production.ts and simulator/scripts/production/.

Passing simulation and DRC proves digital consistency and manufacturability against the encoded rules. Physical timing, signal integrity, power integrity, connector mechanics, and firmware still require validation on fabricated hardware.