CoCoTANG

CoCoTANG

Overview

CoCoTANG upgrades the Radio Shack/Tandy Color Computer with a Tang Nano 20K FPGA board and CoCo 3 video and memory features. It retains the MC6809E CPU and motherboard PIAs while the FPGA implements the GIME video and memory subsystem, HDMI and analog video outputs, and a Glenside-compatible IDE interface backed by a microSD card. It also provides 8 MB of RAM, Orchestra-90 audio with stereo over HDMI, and Tandy Speech/Sound Cartridge (SSC) support.

This repository contains the FPGA sources, KiCad designs, fabrication files, and bill of materials.

The assembly uses a main board for the CPU and Tang Nano 20K, PIA0 and PIA1 adapter boards, and an address mux board that replaces the motherboard 74LS138. An analog video hat and an HDB-DOS ROM cartridge are optional. The render above shows the boards arranged as a PCB panel. HDB-DOS can also be supplied through an FD-502 ROM socket or CoCo SDC flash bank.

The design uses NTSC machine clocking. The GIME's 50 Hz setting remains available, but selecting it does not switch to a PAL crystal. PAL-encoded CVBS/S-Video output is also supported. See Build on macOS or Linux for video targets and the FPGA pin and bus map for hardware connections.

Compatibility

Games

So far, The Contras is the only game found to fail to load in its original form. CoCoTANG's 262.5-scanline timing drifts relative to the original CoCo 3. The resulting timing difference affects an unprotected code section in the game and prevents the original version from loading.

Use the patched version of The Contras instead. This patched version also includes keyboard enhancements.

Multi-Pak Interface and real floppy drives

A Multi-Pak Interface (MPI) holds the cartridge data bus in a way that prevents access to CoCoTANG's internal peripheral registers. With an MPI connected, the internal Glenside IDE, SSC sound/speech, and Orchestra-90 are unavailable. Software that uses these internal devices must be run without the MPI.

An MPI is required to use real floppy drives. Plug the floppy disk controller into the MPI and connect the drives to that controller. This setup uses the external floppy controller, with the internal IDE, SSC, and Orchestra-90 unavailable as described above.

Current FPGA features

• GIME video and memory mapping with 8 MB NoCan3-style RAM support and readable Disto MMU page bits.
• Simultaneous HDMI and analog video, with separate RGB, YPbPr, and CVBS/S-Video build targets.
• Six motherboard RESET selections combining normal, reversed, or disabled artifact colours with SSC sound/speech off or on.
• Tandy Speech/Sound Cartridge PSG, buffered allophones, and ASCII English text-to-speech, alongside the CoCo DAC and Orchestra-90 audio.
• HDMI status labels and an optional analog status banner with a larger font.

Hardware and files

Board quantities and Gerber downloads

For one CoCoTANG installation, you need one main board, one address mux board, and two PIA boards: one for PIA0 and one for PIA1. There are two main-board versions, for motherboard revisions 20261043 and 20261058; choose the version that matches your motherboard. The HDB-DOS cartridge and video hat are optional.

Use the same PIA Gerber ZIP to fabricate both PIA cards. Upload each desired board's ZIP separately to your PCB manufacturer and select the quantities above, subject to the manufacturer's minimum order quantity.

Select 1.2 mm PCB thickness when ordering the adapter boards. The thinner boards reduce the installed profile and help the assembly fit under the keyboard.

Motherboard compatibility

Tandy used several motherboard layouts for the CoCo 2. Identify your motherboard before ordering boards: the CPU and address mux adapters must fit its layout. Only the revisions marked compatible below are currently supported; other layouts may need different adapters.

CoCo 1 compatibility has not yet been tested.

Bill of materials

Both main-board versions (20261043 and 20261058) use the same components and quantities; only the PCB layout differs. Use the fabrication drawing and silkscreen for the version you are assembling.

Logic families and supply voltages

Use HCT parts for the 5 V logic: U9/U16 (74HCT245, depending on the main-board version), U1 (74HCT138), U22 (74HCT11), and U7 (74HCT30). Their TTL-compatible inputs accept the logic levels used at the motherboard interface. The table below gives the manufacturer part numbers, matching DigiKey part numbers, and TSSOP packages.

U3/U6 are 74HC139 decoders powered from 3.3 V, with their select inputs driven by the FPGA. Keep the HC version here: 74HCT139 is specified for a 4.5–5.5 V supply. A 3.3 V supply makes HC139 suitable for this 3.3 V logic domain; it does not turn HC into a generally TTL-compatible family. The KiCad labels now identify both decoder instances as HC139.

The four 74LVC245 buffers on each main board remain LVC parts for the 3.3 V interface; their reference designators are listed for both layouts below. Their TSSOP ordering code is SN74LVC245APWR.

Main board — both versions

The reference columns identify the same components on each layout. Lists follow the same order across both columns. The three interrupt/reset resistors and the additional R/W pull-up are listed separately. The other adapter boards below are shared between both versions.

PIA0 adapter

PIA1 adapter

Address mux board

HDB-DOS cartridge

Analog video board

Boards Interconnection

Assembly

Print the fabrication drawing and use it with the board silkscreen to identify component positions. Check diode orientation before soldering. The main-board bill of materials applies to both supported versions; component positions differ between layouts.

Several adapters have oversized socket holes. They require machined-pin sockets whose pins extend through the adapter to connect to the motherboard socket while holding the original IC above it. Use 1.2 mm PCBs to reduce the overall assembly height and improve clearance under the keyboard.

1. Locate and desolder the CPU, VDG, SAM, PIA0, PIA1, and 74LS138.
2. Keep the SAM, VDG, and 74LS138 as spares; the FPGA replaces their functions.
3. Install sockets in the motherboard. Do not solder the adapter boards directly to it.
4. Check clearance around the adapters. Some original capacitors marked 104 are oversized, and nearby radial capacitors may also interfere. Where necessary, desolder and reposition their leads before bending the capacitors closer to the motherboard.
5. Populate the adapter boards, checking diode orientation. Configure each PIA adapter as described in PIA adapter configuration.
6. Modify pin 5 of each joystick connector and wire it to the PIA0 adapter as described in Joystick second-button support.
7. Fit the CPU and PIAs to their adapters, install the adapters, and connect the boards as shown in the installed prototype.
8. Program the Tang Nano 20K with the desired .fs bitstream and CoCo 3 ROM, following the programming instructions below.
9. If using the optional HDB-DOS cartridge, program its EEPROM with hdblba.rom using an EEPROM programmer.
10. Turn on the computer. The boot screen should look like the example below.

Assembled boards

The photos below show the component population and header placement, in assembly order. Front and back views are included where available.

Main board

The main board carries the CPU socket, Tang Nano 20K headers, bus buffers, and connections to the other adapters. The photos show the assembled board before fitting the CPU and FPGA module. Choose the layout that matches your motherboard revision.

Front	Back

ADDRMUX board

The address mux adapter plugs into the motherboard's former 74LS138 position and connects to the main board. Leave the 74LS138 socket on the ADDRMUX adapter empty; do not reinstall the original IC in it. The adapter's onboard logic replaces its function.

PIA0 adapter

Populate the logic IC, diodes, capacitors, and headers required for PIA0, and select the PIA0 jumper setting. The external keyboard header is fitted only on this adapter. These photos show the board before installing the PIA.

Front	Back

PIA1 adapter

PIA1 uses the same PCB with the PIA1 jumper setting. Fit the socket and required signal header; leave the PIA0-only logic, diodes, capacitors, and external keyboard header unpopulated. These photos show the board before installing the PIA.

Front	Back

AVIDEO board

The optional analog audio/video board can be mounted in the original RF modulator/shield location. Enlarge the opening in the CoCo's cover to clear the 5-pin DIN connector. Use pin headers on the back of the AVIDEO PCB to secure it to the CoCo motherboard, as shown in the back view.

Front	Back / mounting headers

The completed installation brings the main board, ADDRMUX, PIA adapters, and AVIDEO board together:

Complete assembly and umbilical cables

The photo below shows the fully assembled main board, PIA0, PIA1, ADDRMUX, AVIDEO, and external keyboard companion with their umbilical cables connected. Use it as an overview alongside the pin and bus map when connecting the boards.

AVIDEO mounting and case opening

Prepare the RF modulator area

With the original RF module removed, prepare its mounting position for AVIDEO. Remove the plastic spacers from the mounting header pins so the AVIDEO PCB can sit close to the motherboard. Leave the metal pins in place for soldering the board, as shown below.

Trim the underside and solder the board close to the motherboard

Clip all excess component leads and header-pin ends on the underside of AVIDEO, and remove excess solder that would prevent the board from sitting close to the motherboard. Retain the mounting pins needed to secure it. Fit the board over the prepared RF-area mounting pins, align the DIN-5 connector with the rear of the case, and solder the mounting pins with the PCB close to the motherboard. Keep clearance between the underside solder joints and the motherboard.

Trimmed AVIDEO underside	Mounted board, side view

Copy an existing opening onto tape

Use a neighboring DIN connector opening as a template. Apply masking tape over it and copy its outline by trimming the tape to match the opening. Peel off the tape and stick it over the original TO TV opening, aligning the bottom edge and checking its position against the installed AVIDEO connector. The transferred outline marks the enlarged opening needed for the DIN-5 plug.

Copy the opening onto masking tape	Transfer the tape to the TO TV opening

Enlarge the opening with a Dremel bit

Remove the cover from the computer before machining it. Use a Dremel or similar rotary tool with a bit like the one shown to enlarge the opening to the tape outline. Remove material gradually, smooth the edges, and check the fit of the DIN-5 plug. Clear away the plastic debris before refitting the cover.

Rotary-tool bit	Finished opening

Close the lid and connect the DIN-5 cable

Refit the cover, checking that the internal cables are clear of its edges. The DIN-5 plug should fit through the enlarged opening and seat fully in the AVIDEO socket. The finished installation below shows the closed lid, connected DIN-5 cable, and external keyboard companion.

PIA adapter configuration

Both PIAs use the same adapter PCB, but they require different component populations and jumper settings:

• PIA0: populate the adapter's logic IC, diodes, and capacitors listed in the PIA0 bill of materials, and set the selection jumper to PIA0. The photo below shows PIA0 fitted with the SC67331P chip.
• PIA1: fit the PIA socket; the additional logic IC, diodes, and capacitors are not required. This adapter brings out only two signal pins. Set its selection jumper to PIA1.

The new PIA PCB also includes a pinout for an external keyboard. Populate and connect the external keyboard header only on PIA0.

External keyboard companion

The optional four-key companion board uses 4 Cherry MX key switches, labeled CTRL, ALT, F1, and F2, and connects to the external keyboard header on PIA0. The photo shows the assembled companion beside the CoCo 2's built-in keyboard, with its cable attached. The PCB fabrication files are available as gerber_extkey.zip.

Joystick second-button support

To support a second button on each joystick, disconnect pin 5 of each joystick connector from its original motherboard ground connection. Desolder the pin, pull it clear of the motherboard, and bend it upward as shown below. Keep the lifted pin clear of its original pad.

Use two jumper wires, one from each lifted pin, to connect the joystick second-button signals to the corresponding connections on the PIA0 adapter (SC67331P in the PIA photo above). To attach a jumper lead to a lifted pin, remove the plastic housing at that end and gently widen the metal contact to fit.

CPU choice: MC6809E or HD6309E

While the CPU is removed, you can replace the MC6809E with an HD6309E. NitrOS-9 supports the HD6309's native mode, and compatible applications can use its additional instructions. Choose the disk image that matches your installed CPU.

Audio / Video

HDMI

You can use this HDMI flat cable to expose the HDMI port outside the CoCo2 case. Being as flat just let it go through some port. Choose a model like A1-A4.

Audio Video Board

The optional CoCoTANG Audio/Video board provides a 5-pin DIN output and fits in the original RF modulator/shield location. Enlarge the cover opening for the connector and secure the PCB to the motherboard using the rear pin headers shown in the AVIDEO assembly photos. Follow the illustrated mounting and case-opening guide to prepare the RF area and enlarge the cover opening.

The revised J24 DIN-5 connector follows the Atari 800XL monitor pin assignment, with chroma connected to pin 5. The diagram shows the female socket viewed from the front, looking into the connector on the computer, with the keyway at the bottom. The cable plug's mating-face view is mirrored.

Select the matching FPGA video image; the same physical pins carry different signals in each mode. For composite, use pins 4 (video), 3 (audio), and 2 (ground). For S-Video, use 1 (Y), 5 (C), and 2 (ground), with audio on pin 3.

For an example lead, see this 5-pin DIN to four-RCA cable; select the 5-pin version and verify its wiring against the table above.

Use an Atari 800XL-style monitor cable wired to this table for CVBS/S-Video. RGB and YPbPr need cables wired for their respective columns. Check the actual DIN pin connections rather than relying on RCA plug colors or the connector's pin count. This pinout applies to the revised AVIDEO PCB; check older boards before reusing a cable.

The assignments above match J24's current PCB nets: 1=G_Y, 2=GND, 3=AUDIO_RCA, 4=R_CVBS, 5=B_CHR. The diagram's editable source is din5-av-pinout.svg. For the Atari monitor-port reference, see the Atari 800XL service manual and Atari connector FAQ. CoCoTANG supplies chroma on pin 5, which was unconnected on many original 800XL machines.

Display compatibility and PVM connections

YPbPr component: use a TV or monitor that accepts 15 kHz standard-definition 480i/240p signals over its component inputs, such as a compatible PVM or a CRT TV with YPbPr inputs. Check that the particular display accepts 240p; support for 480i alone does not guarantee it. Connect DIN pin 1 to Y, 5 to Pb, and 4 to Pr, with pin 3 for audio.

RGB with sync on green (SoG): use a cable wired specifically for CoCoTANG's RGB pinout and a display that accepts sync on green. On a compatible PVM, you can instead use the same 5-pin DIN to four-RCA lead linked above, with RCA-to-BNC adapters on the three video leads:

Select RGB on the PVM and choose internal sync (INT), or turn EXT SYNC off, so it takes sync from green. The fourth RCA lead carries audio; a separate external-sync connection is not needed. For YPbPr, use the same three video connections but select component / YPbPr instead. Control names vary by model; see, for example, the Sony PVM-D14L5A/D20L5A operating instructions.

Preparing the microSD card

Download the appropriate CPU version of the CF disk image and write it to the microSD card used by CoCoTANG. These images require HDB-DOS, supplied by the optional cartridge or another supported ROM source.

On Linux, identify and unmount the card, then write the image to the whole device, replacing /dev/sdX with the correct device path:

sudo dd if=CF_6309.IMG of=/dev/sdX bs=1M
sync

The example uses the HD6309 image. Writing the image replaces the card's contents, so verify the destination device before running the command.

Artifact colours and SSC sound/speech

The standard build includes the Tandy Speech/Sound Cartridge (SSC) PSG and speech engine. SSC always starts disabled at cold boot. Press the CoCo motherboard RESET to advance through these selections:

The next RESET returns to ARTIFACT NORMAL with SSC disabled. RESET is debounced, and holding it down advances only once. Disabled SSC stays silent, holds both synthesizers in reset, and leaves $FF7D/$FF7E available to the motherboard/cartridge bus. Software cannot enable SSC by writing its registers while an SSC-off selection is active.

HDMI shows the selected label for about four seconds. The analog banner is optional and off by default: set ENABLE_ANALOG_BANNER=1 in fpga/src/top_coco3.v and rebuild to include it. Its font is doubled in both dimensions, with each font row occupying two analog scanlines. This applies to RGB, YPbPr, CVBS, and S-Video; the HDMI label keeps its original size.

When SSC is selected, software resets its interface by writing 1 then 0 to $FF7D. $FF7E accepts commands/data and returns status; bit 7 high means ready. The implementation supports direct PSG register writes, buffered sound events/register streams, buffered AL2 allophones, and immediate ASCII text terminated by carriage return. English text uses NRL letter-to-sound rules; this is command-level compatibility rather than a TMS7040 CPU emulation. The speech interface source documents the supported commands.

PSG and speech are combined and mixed into both HDMI channels and the physical mono output at 1.5× gain (about +3.5 dB). The CoCo DAC and Orchestra-90 gains are unchanged. The final sum saturates at the signed PCM limits instead of wrapping, and disabling SSC clamps its contribution to silence.

In custom builds, ENABLE_SSC_SPEECH=0 removes speech while retaining the PSG; ENABLE_SSC_PSG=0 removes both SSC engines and restores the three artifact-only reset selections. make test-ssc-toggle checks the real top-level reset cycle, disabled bus/audio behavior, and both analog-banner settings using Gowin's installed simulation library.

Orchestra-90 audio

Orchestra-90 audio is enabled by default and provides two 8-bit DACs without the cartridge ROM. Software writes unsigned samples to $FF7A (left) and $FF7B (right); 128 is the digital midpoint. Each channel holds its last sample until the next write. These are write-only DACs: reading the addresses does not change their values or provide readback.

Orchestra-90 requires no additional cartridge ROM or audio hardware. It is enabled by default in every normal machine image; no separate Orchestra-90 build is needed.

HDMI sends stereo PCM at 48 kHz. The existing CoCo PIA DAC is mixed equally into both channels at its normal gain; each Orchestra-90 DAC contributes at half gain, and the mixer clips at the signed PCM limits to prevent overflow. Both Orchestra-90 channels reset to the midpoint so they contribute silence before software uses them. The analog audio_out pin carries a mono mix of both Orchestra-90 channels and the CoCo PIA DAC. Each Orchestra-90 channel contributes at quarter gain to this downmix, while the CoCo PIA DAC keeps its normal gain; the sum is clipped before conversion to the physical 8-bit sigma-delta DAC.

To omit Orchestra-90 audio in a custom build, set the top_coco3 parameter ENABLE_ORCHESTRA90=0. Address and channel assignments follow XRoar's Orchestra-90 documentation and MAME's Orchestra-90 implementation.

Build on macOS or Linux

1. Download GOWIN EDA Education for your OS from Gowin's official download page (an account may be required). Install the full EDA package, not only Gowin Programmer. The Education edition is intended for noncommercial education/research; check Gowin's current terms for your use.

2. Install openFPGALoader and, for simulation, Icarus Verilog (iverilog and vvp). On macOS, brew install openfpgaloader icarus-verilog is one option. On Debian/Ubuntu, sudo apt install openfpgaloader iverilog is one option. Linux may also need the openFPGALoader udev rules for non-root USB access.

3. From the FPGA directory, build and check the routed design:

   cd fpga
   make test
   make rebuild
   make timing

   make test is optional for building the bitstream. Its current recipes write simulation executables to /private/tmp, so on Linux that directory must exist and be writable if you run the tests; make rebuild and make timing do not need it.

The output is fpga/impl/pnr/CoCoTANG.fs. make rebuild always runs synthesis and place-and-route; make build rebuilds only when Make considers an input newer than the bitstream. The Makefile expects Gowin at /Applications/GowinIDE.app/Contents/Resources/Gowin_EDA/IDE on macOS or /opt/Gowin/IDE on Linux. If yours is elsewhere, pass GOWIN_IDE=/path/to/Gowin_EDA/IDE to Make.

Select an analog video output

Each mode has its own bitstream and fixed video-mode setting, independent of the default ANALOG_VIDEO_MODE in src/top_coco3.v:

Run these commands from fpga/. To build without programming, use make build-rgb, make build-ypbpr, or make build-cvbs. Use make rebuild-rgb, make rebuild-ypbpr, or make rebuild-cvbs to force a rebuild, and the corresponding make timing-rgb, make timing-ypbpr, or make timing-cvbs to check the routed timing. The reprogram-* targets never rebuild; their named image must already exist.

The artifact/SSC status banner is off on analog outputs by default. Set ENABLE_ANALOG_BANNER=1 in fpga/src/top_coco3.v and rebuild to enable its larger font in any analog video mode. The HDMI status label and reset selector are always available.

Rebuild every variation

Run these commands from fpga/:

make build-all     # build missing or outdated images
make rebuild-all   # force synthesis and place-and-route for every image

Both targets cover six images: standard, RGB, YPbPr, CVBS/S-Video, PAL, and the standalone bus tester. The NTSC S-Video targets share the confirmed CVBS image, so it is built once. Logger/debug images are excluded.

Builds run sequentially, even with make -j, because Gowin shares the impl/ directory between projects. Every variant is attempted, and routed timing is checked after each successful build. The target returns a failure status if any build or timing check fails; it never programs the board or changes placement settings. Per-variant logs and summary.json are written to fpga/impl/build-all/ or fpga/impl/rebuild-all/.

Debug and bus testing

The standalone bus tester is included in the aggregate builds. The normal production images keep the bus logger disabled; logger/debug projects are not restored by the aggregate targets.

For board bring-up, make data-test-program-sram builds the standalone bus tester if needed and loads it into FPGA SRAM for a temporary test. Use make data-test-program to store the tester in flash. It holds the CPU in reset and displays the data sweep and bus readback over HDMI. See the bus tester notes for controls and verification commands.

Program on macOS or Linux

Connect the Tang Nano 20K by USB. The FPGA configuration and CoCo 3 ROM are two separate writes to the module's external SPI flash:

cd fpga
make program     # builds if needed, then writes persistent FPGA configuration
make rom         # writes the ROM at 0x100000; needed for first setup

make reprogram flashes the existing bitstream without rebuilding. These Make targets use openFPGALoader's tangnano20k board support. The ROM offset is set by ROM_OFFSET=1048576 in the Makefile and by the FPGA flash loader; do not write the ROM at address zero, or it will overwrite the FPGA configuration. After both writes, power-cycle the board. The FPGA holds the CPU until its clocks, SDRAM, and ROM load are ready.

Test the bus and addresses in SRAM

Run make data-test-program-sram from fpga/ to build the standalone bus tester if needed and load CoCoTANG-data-test.fs into the FPGA's volatile SRAM. The tester holds the CPU in reset and displays the data sweep, address bus readback, and control signals over HDMI. It does not need a CoCo 3 ROM.

This leaves the stored FPGA configuration and ROM unchanged. Power-cycling restores the configuration stored in flash.

Using the tester to diagnose the board

The tester helps locate missing connections, solder bridges, swapped bus lines, and faults in the bus buffers or address mux. FPGA IN shows the data bus at the FPGA side of the data transceiver. CPU ADDRESS and the A15–A8 / A7–A0 fields show the address sampled through the mux; the tester reads these lines rather than driving them.

Use the Tang Nano's S2 button to switch between sweep and hold. In hold mode, S1 advances the data byte and S code by one; in sweep mode, S1 restarts both at zero. The S code controls motherboard device selection, so hold mode is useful when probing a fixed condition.

Prepare for manual pin testing: turn off the computer and remove the CPU before attaching jumpers. Removing it lets you set each address line independently without fighting the CPU's outputs. Make connections on the CPU/motherboard side of the adapters, using motherboard ground and the board's normal logic levels; do not apply 5 V directly to Tang Nano pins.

Test each data line:

1. Load the tester with make data-test-program-sram and connect HDMI.
2. Ground R/W for manual data-input testing. Check that the screen shows RW:0 and DRIVE:0 before grounding any data pin. R/W low releases the FPGA's data outputs and selects the input direction through the data transceiver.
3. With the other data inputs at a known high level through suitable pull-ups, ground D0 and check that only bit 0 of FPGA IN goes low. The expected byte is $FE.
4. Move the ground connection to D1 through D7, one pin at a time. The expected bytes are $FD, $FB, $F7, $EF, $DF, $BF, and $7F. Remove each connection before testing the next pin. These values assume all ungrounded data lines remain high; floating inputs are not a reliable reference.

DATA OUT is the sweep generator's requested byte. While DRIVE:0, it is not being driven onto the data bus, so it does not need to match FPGA IN. A pin that does not change its displayed bit suggests an open connection or buffer problem; a different bit changing suggests swapped wiring, and two bits changing together suggests a short.

Test each address line:

1. Keep the CPU removed and R/W grounded. Establish known levels on A0–A15 using the board's pull-ups or suitable test pull-ups.
2. Ground A0, then A1 through A15, one at a time. Check that only the corresponding bit changes in CPU ADDRESS and the address bit fields. With all other address lines high, grounding A0 gives $FFFE, grounding A1 gives $FFFD, and grounding A15 gives $7FFF.
3. Check MUX0 LOW for A0–A7 and MUX1 HIGH for A8–A15. The high-address mux uses a remapped bit order; use the decoded address fields to identify CPU address bits.

A line that never changes can indicate an open joint, missing connection, or buffer/mux fault. An unexpected address bit changing can indicate incorrect wiring or an address-remap problem. The display shows the FPGA's sampled result; a meter or logic analyzer at the CPU socket and buffer pins helps locate where the signal is lost.

Turn off the computer before removing the test jumpers or reinstalling the CPU. Remove the R/W ground connection before returning to normal operation. Power-cycling also restores the FPGA image stored in flash.

Windows: Gowin Programmer

For Windows, use the Gowin Programmer supplied with Gowin EDA Education (or Gowin's standalone Programmer). The repository's Makefile is written for macOS/Linux and uses openFPGALoader; it is not a native Windows programming recipe. Gowin's Programmer User Guide describes the device-configuration dialog.

1. Install Gowin's USB programmer driver, connect the Tang Nano 20K, and open Gowin Programmer. Scan the cable/device; the board uses a GW2AR-18C in a QN88 package.
2. To test without preserving the configuration after power-off, choose SRAM Mode → SRAM Program and select fpga/impl/pnr/CoCoTANG.fs.
3. To make the FPGA configuration persistent, open Edit → Configure Device, choose External Flash Mode, select exFlash Erase, Program thru GAO-Bridge (or its verify variant), choose fpga/impl/pnr/CoCoTANG.fs, set External Flash Options → Start Address to 0x000000, save, then click Program/Configure.
4. Program the ROM as a separate raw binary operation: configure External Flash Mode, choose exFlash C Bin Erase, Program thru GAO-Bridge (or its verify variant), select fpga/roms/coco3.rom under FW/MCU/Binary Input Options → Firmware/Binary File, choose Generic Flash if a flash-device choice is required, and set External Flash Options → Start Address to 0x100000. Save and program. The dialog wording varies between Gowin releases; the important distinction is the raw-binary operation and the 1 MiB start address.
5. Power-cycle the board. If the FPGA configures but the CPU does not start, recheck the ROM write and its offset.

Windows USB driver choice: Gowin Programmer and openFPGALoader may require different USB drivers. The normal Windows path above uses Gowin's driver. If you choose to use openFPGALoader on Windows instead, install its Windows build and use Zadig to bind WinUSB to the Tang Nano 20K's programming/JTAG interface (enable Options → List All Devices if necessary). Check the device/interface identity before clicking Install/Replace Driver—do not replace an unrelated USB interface. Switching to WinUSB can stop Gowin Programmer from seeing the board; restore the Gowin driver in Device Manager or reinstall it when returning to Gowin Programmer. libusb's Windows guidance recommends WinUSB for libusb applications.

Project status

This is an actively developed hardware/RTL project. Review the pin and bus map, fabrication drawing, and KiCad files before building hardware. Flashing a new FPGA image or ROM changes the board's nonvolatile contents; keep a known-good image available while experimenting.

Showcase

Games, NitrOS-9, and a graphics demo running on CoCoTANG:

Calixto Island	Contras

NitrOS-9	Sock Master's Drive Thru demo